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AgeCommit message (Expand)AuthorFilesLines
2019-07-22Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)Tim Newsome2-9/+13
2019-05-14Implement debug hasel support (#287)Tim Newsome2-10/+14
2018-03-06Fix install of a missed header from debug_rom.Prashanth Mundkur2-3/+3
2018-03-06Fix a missed header file in the softfloat include install.Prashanth Mundkur1-23/+0
2017-06-08`make clean && make` works again in debug_romTim Newsome2-2/+2
2017-04-18debug: Add fence and fence.i to ensure Debug RAM is ready.Megan Wachs2-26/+14
2017-04-18debug: Checkpoint which somewhat works with OpenOCD v13, but still has some b...Megan Wachs1-0/+1
2017-04-17debug: move the debug_rom defines to a seperate fileMegan Wachs2-5/+15
2017-04-17debug: Use more unique debug ROM namesMegan Wachs3-16/+32
2017-04-17debug: Use a more practical debug ROMMegan Wachs4-161/+83
2016-09-02Rebuild debug ROM because CSR encoding changed.Tim Newsome1-2/+2
2016-06-22Parameterize debug ROM contents on XLENAndrew Waterman4-28/+81
2016-06-22Remove fence.i from debug ROMAndrew Waterman1-1/+0
2016-06-09Fix 2 bugs in Debug ROM: (#52)Tim Newsome2-10/+12
2016-06-03DCSR cause was moved, bug debug ROM wasn't updatedTim Newsome2-3/+3
2016-06-01Add gitignoreAndrew Waterman1-0/+2
2016-06-01Move sethaltnot and cleardebint.Tim Newsome2-4/+4
2016-05-24New encoding.h for new CSR addresses.Tim Newsome2-5/+5
2016-05-24Move cleardebint, per spec.Tim Newsome2-3/+3
2016-05-23Change DCSR bits to match spec.Tim Newsome2-22/+14
2016-05-23Move debug rom link map to the right place.Tim Newsome2-2/+2
2016-05-23Use fence.i in Debug ROM.Tim Newsome2-9/+10
2016-05-23Add dret.Tim Newsome2-3/+2
2016-05-23Implement single memory read access.Tim Newsome2-24/+29
2016-05-23Exceptions in Debug Mode, stay in Debug Mode.Tim Newsome2-16/+28
2016-05-23Have Debug memory kind of working again.Tim Newsome2-14/+13
2016-05-23Fix race using fence.Tim Newsome2-21/+16
2016-05-23Refactor how we track in-progress operations.Tim Newsome1-0/+1
2016-05-23processor_t unfriends gdbserver_t.Tim Newsome2-2/+2
2016-05-23Add debug_module bus device.Tim Newsome3-15/+14
2016-05-23ROM -> RAM -> ROM, waiting for debug int.Tim Newsome2-2/+2
2016-05-23Jump to the correct (temporary) Debug RAM address.Tim Newsome2-6/+7
2016-05-23Clean up how Debug ROM is included.Tim Newsome4-0/+154
2016-05-23Can jump to and execute Debug ROM.Tim Newsome4-154/+0
2016-05-23Check in compiled debug ROM.Tim Newsome2-3/+24
2016-05-23Add debug rom code.Tim Newsome3-0/+133
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