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2020-04-14rvv: add float conversion for rtz variantsChih-Min Chao9-1/+95
2020-04-14rvv: add new vcsr vector csrChih-Min Chao3-19/+31
2020-04-14Handle misaligned memories by aligning them, rather than erroringAndrew Waterman1-1/+16
2020-04-14Revert "rvv: support simulations with mem size <4K"Chih-Min Chao1-1/+1
2020-04-10rvv: remove unecessary initializationChih-Min Chao1-1/+0
2020-04-10rvv: vslide[1]up now allows mask overlap when LMUL=1Chih-Min Chao3-3/+3
2020-04-10rvv: fix index segment load overlapping checkChih-Min Chao1-5/+7
2020-04-10op: update CSRChih-Min Chao4-14/+40
2020-04-10rvv: missing vector enabling check for mask operationChih-Min Chao1-0/+1
2020-04-07rvv: support simulations with mem size <4KDave.Wen1-1/+1
2020-04-05Fix debug segfault by partially reverting #409Andrew Waterman1-2/+3
2020-04-05option: flag x extension without loading shared lib (#439)Chih-Min Chao1-1/+5
2020-04-05Deny hart access to debug CSRs when not in D-modeAndrew Waterman1-0/+8
2020-04-05Assert that debug_module is initialized correctly. (#437)Tim Newsome1-0/+1
2020-04-05When enabling the debug module, poll til it's really enabledAndrew Waterman1-0/+2
2020-04-05FESVR: ensure dmactive is 1 before reading debug module registersMegan Wachs1-3/+3
2020-04-05Write execution logs to a named log file (#409)Rupert Swarbrick8-83/+152
2020-04-05Allow PATH lookup for executing dtc (#432)綺麗な賢狼ホロ1-1/+1
2020-04-05Don't acquire load reservation in the event of a faultAndrew Waterman2-2/+4
2020-04-05Fix hard-coded path to DTC that breaks packaging (#428)Joel Sherrill2-15/+3
2020-04-05ebreak should write mtval with 0, not pcAndrew Waterman3-3/+3
2020-04-05fixed htif exception typo (#423)Dai chou1-1/+1
2020-03-27rvv: fix int_max/min value calculationChih-Min Chao8-23/+26
2020-03-26rvv: fix vssraa.vi e64 corner caseChih-Min Chao1-1/+1
2020-03-26rvv: check vlen == slenChih-Min Chao1-0/+2
2020-03-24rvv: fix vmv reg checking failureChih-Min Chao3-1/+6
2020-03-24add f16_classifyHan-Kuan Chen2-0/+37
2020-03-23rvv: restrict segment load register ruleChih-Min Chao4-3/+4
2020-03-23sf: simplify sNaN handling for fmax and fminChih-Min Chao1-24/+12
2020-03-23rvv: fix WARL behavior for vxsat and vxrmChih-Min Chao1-2/+2
2020-03-23use riscv-vector-tests ciHan-Kuan Chen1-22/+0
2020-03-17remove docker and use new pathHan-Kuan Chen3-23/+1
2020-03-17rvv: fix vdiv corner caseChih-Min Chao2-2/+2
2020-03-17rvv: sf: handle signaling NaN for fmax/fminChih-Min Chao1-2/+14
2020-03-16commitlog: fix build failedChih-Min Chao1-4/+6
2020-03-16commitlog: fix wrong dump when exception occurChih-Min Chao2-4/+9
2020-03-12rvv: commitlog: fix vrgather_vv dumpChih-Min Chao1-4/+4
2020-03-12rvv: fix vfmv.f.s and vfmv.s.fChih-Min Chao2-22/+21
2020-03-11commitlog: fix missing dump for some instructionsChih-Min Chao8-29/+32
2020-03-11rvv: respect vstart and vl for vfmv.s.fChih-Min Chao1-19/+22
2020-03-08Make debug printfs only show in debug builds. (#414)Andrew Waterman1-6/+6
2020-03-08Don't clobber trigger types when initializing stateAndrew Waterman1-1/+1
2020-03-05rvv: fix vf(w)redsum option parsing bugZhen Wei1-4/+5
2020-03-05rvv: avoid redundant std::string comparisonZhen Wei4-20/+40
2020-03-05rvv: update the vector fredsum algorithmZhen Wei1-15/+23
2020-03-05rvv: import parallel vf(w)redsum hardware impl.Zhen Wei7-16/+118
2020-03-03commitlog: fix conditional building errorChih-Min Chao1-1/+3
2020-03-03op: update encodingChih-Min Chao1-315/+372
2020-03-03commitlog: enhance vector dumpChih-Min Chao2-5/+15
2020-03-03rvv: handle middle value of vslidedown.vxChih-Min Chao1-1/+1
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