diff options
| -rw-r--r-- | riscv/encoding.h | 18 | ||||
| -rw-r--r-- | riscv/insns/vfcvt_rtz_x_f_v.h | 10 | ||||
| -rw-r--r-- | riscv/insns/vfcvt_rtz_xu_f_v.h | 10 | ||||
| -rw-r--r-- | riscv/insns/vfncvt_rtz_x_f_w.h | 11 | ||||
| -rw-r--r-- | riscv/insns/vfncvt_rtz_xu_f_w.h | 11 | ||||
| -rw-r--r-- | riscv/insns/vfwcvt_rtz_x_f_v.h | 11 | ||||
| -rw-r--r-- | riscv/insns/vfwcvt_rtz_xu_f_v.h | 11 | ||||
| -rw-r--r-- | riscv/riscv.mk.in | 6 | ||||
| -rw-r--r-- | spike_main/disasm.cc | 8 |
9 files changed, 95 insertions, 1 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index 2729f23..c052c6f 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -1052,6 +1052,10 @@ #define MASK_VFCVT_F_XU_V 0xfc0ff07f #define MATCH_VFCVT_F_X_V 0x88019057 #define MASK_VFCVT_F_X_V 0xfc0ff07f +#define MATCH_VFCVT_RTZ_XU_F_V 0x88031057 +#define MASK_VFCVT_RTZ_XU_F_V 0xfc0ff07f +#define MATCH_VFCVT_RTZ_X_F_V 0x88039057 +#define MASK_VFCVT_RTZ_X_F_V 0xfc0ff07f #define MATCH_VFWCVT_XU_F_V 0x88041057 #define MASK_VFWCVT_XU_F_V 0xfc0ff07f #define MATCH_VFWCVT_X_F_V 0x88049057 @@ -1062,6 +1066,10 @@ #define MASK_VFWCVT_F_X_V 0xfc0ff07f #define MATCH_VFWCVT_F_F_V 0x88061057 #define MASK_VFWCVT_F_F_V 0xfc0ff07f +#define MATCH_VFWCVT_RTZ_XU_F_V 0x88071057 +#define MASK_VFWCVT_RTZ_XU_F_V 0xfc0ff07f +#define MATCH_VFWCVT_RTZ_X_F_V 0x88079057 +#define MASK_VFWCVT_RTZ_X_F_V 0xfc0ff07f #define MATCH_VFNCVT_XU_F_W 0x88081057 #define MASK_VFNCVT_XU_F_W 0xfc0ff07f #define MATCH_VFNCVT_X_F_W 0x88089057 @@ -1074,6 +1082,10 @@ #define MASK_VFNCVT_F_F_W 0xfc0ff07f #define MATCH_VFNCVT_ROD_F_F_W 0x880a9057 #define MASK_VFNCVT_ROD_F_F_W 0xfc0ff07f +#define MATCH_VFNCVT_RTZ_XU_F_W 0x880b1057 +#define MASK_VFNCVT_RTZ_XU_F_W 0xfc0ff07f +#define MATCH_VFNCVT_RTZ_X_F_W 0x880b9057 +#define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f #define MATCH_VFSQRT_V 0x8c001057 #define MASK_VFSQRT_V 0xfc0ff07f #define MATCH_VFCLASS_V 0x8c081057 @@ -2257,17 +2269,23 @@ DECLARE_INSN(vfcvt_xu_f_v, MATCH_VFCVT_XU_F_V, MASK_VFCVT_XU_F_V) DECLARE_INSN(vfcvt_x_f_v, MATCH_VFCVT_X_F_V, MASK_VFCVT_X_F_V) DECLARE_INSN(vfcvt_f_xu_v, MATCH_VFCVT_F_XU_V, MASK_VFCVT_F_XU_V) DECLARE_INSN(vfcvt_f_x_v, MATCH_VFCVT_F_X_V, MASK_VFCVT_F_X_V) +DECLARE_INSN(vfcvt_rtz_xu_f_v, MATCH_VFCVT_RTZ_XU_F_V, MASK_VFCVT_RTZ_XU_F_V) +DECLARE_INSN(vfcvt_rtz_x_f_v, MATCH_VFCVT_RTZ_X_F_V, MASK_VFCVT_RTZ_X_F_V) DECLARE_INSN(vfwcvt_xu_f_v, MATCH_VFWCVT_XU_F_V, MASK_VFWCVT_XU_F_V) DECLARE_INSN(vfwcvt_x_f_v, MATCH_VFWCVT_X_F_V, MASK_VFWCVT_X_F_V) DECLARE_INSN(vfwcvt_f_xu_v, MATCH_VFWCVT_F_XU_V, MASK_VFWCVT_F_XU_V) DECLARE_INSN(vfwcvt_f_x_v, MATCH_VFWCVT_F_X_V, MASK_VFWCVT_F_X_V) DECLARE_INSN(vfwcvt_f_f_v, MATCH_VFWCVT_F_F_V, MASK_VFWCVT_F_F_V) +DECLARE_INSN(vfwcvt_rtz_xu_f_v, MATCH_VFWCVT_RTZ_XU_F_V, MASK_VFWCVT_RTZ_XU_F_V) +DECLARE_INSN(vfwcvt_rtz_x_f_v, MATCH_VFWCVT_RTZ_X_F_V, MASK_VFWCVT_RTZ_X_F_V) DECLARE_INSN(vfncvt_xu_f_w, MATCH_VFNCVT_XU_F_W, MASK_VFNCVT_XU_F_W) DECLARE_INSN(vfncvt_x_f_w, MATCH_VFNCVT_X_F_W, MASK_VFNCVT_X_F_W) DECLARE_INSN(vfncvt_f_xu_w, MATCH_VFNCVT_F_XU_W, MASK_VFNCVT_F_XU_W) DECLARE_INSN(vfncvt_f_x_w, MATCH_VFNCVT_F_X_W, MASK_VFNCVT_F_X_W) DECLARE_INSN(vfncvt_f_f_w, MATCH_VFNCVT_F_F_W, MASK_VFNCVT_F_F_W) DECLARE_INSN(vfncvt_rod_f_f_w, MATCH_VFNCVT_ROD_F_F_W, MASK_VFNCVT_ROD_F_F_W) +DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W) +DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W) DECLARE_INSN(vfsqrt_v, MATCH_VFSQRT_V, MASK_VFSQRT_V) DECLARE_INSN(vfclass_v, MATCH_VFCLASS_V, MASK_VFCLASS_V) DECLARE_INSN(vfwadd_vv, MATCH_VFWADD_VV, MASK_VFWADD_VV) diff --git a/riscv/insns/vfcvt_rtz_x_f_v.h b/riscv/insns/vfcvt_rtz_x_f_v.h new file mode 100644 index 0000000..b83365f --- /dev/null +++ b/riscv/insns/vfcvt_rtz_x_f_v.h @@ -0,0 +1,10 @@ +// vfcvt.x.f.v vd, vd2, vm +VI_VFP_VF_LOOP +({ + softfloat_roundingMode = softfloat_round_minMag; + P.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, STATE.frm, true); +}, +{ + softfloat_roundingMode = softfloat_round_minMag; + P.VU.elt<int64_t>(rd_num, i) = f64_to_i64(vs2, STATE.frm, true); +}) diff --git a/riscv/insns/vfcvt_rtz_xu_f_v.h b/riscv/insns/vfcvt_rtz_xu_f_v.h new file mode 100644 index 0000000..60cf8c8 --- /dev/null +++ b/riscv/insns/vfcvt_rtz_xu_f_v.h @@ -0,0 +1,10 @@ +// vfcvt.xu.f.v vd, vd2, vm +VI_VFP_VV_LOOP +({ + softfloat_roundingMode = softfloat_round_minMag; + P.VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, STATE.frm, true); +}, +{ + softfloat_roundingMode = softfloat_round_minMag; + P.VU.elt<uint64_t>(rd_num, i) = f64_to_ui64(vs2, STATE.frm, true); +}) diff --git a/riscv/insns/vfncvt_rtz_x_f_w.h b/riscv/insns/vfncvt_rtz_x_f_w.h new file mode 100644 index 0000000..3cbc684 --- /dev/null +++ b/riscv/insns/vfncvt_rtz_x_f_w.h @@ -0,0 +1,11 @@ +// vfncvt.x.f.v vd, vs2, vm +VI_CHECK_SDS(false); +if (P.VU.vsew == e32) + require(p->supports_extension('D')); + +VI_VFP_LOOP_BASE + softfloat_roundingMode = softfloat_round_minMag; + auto vs2 = P.VU.elt<float64_t>(rs2_num, i); + P.VU.elt<int32_t>(rd_num, i, true) = f64_to_i32(vs2, STATE.frm, true); + set_fp_exceptions; +VI_VFP_LOOP_END diff --git a/riscv/insns/vfncvt_rtz_xu_f_w.h b/riscv/insns/vfncvt_rtz_xu_f_w.h new file mode 100644 index 0000000..4c5e785 --- /dev/null +++ b/riscv/insns/vfncvt_rtz_xu_f_w.h @@ -0,0 +1,11 @@ +// vfncvt.xu.f.v vd, vs2, vm +VI_CHECK_SDS(false); +if (P.VU.vsew == e32) + require(p->supports_extension('D')); + +VI_VFP_LOOP_BASE + softfloat_roundingMode = softfloat_round_minMag; + auto vs2 = P.VU.elt<float64_t>(rs2_num, i); + P.VU.elt<uint32_t>(rd_num, i, true) = f64_to_ui32(vs2, STATE.frm, true); + set_fp_exceptions; +VI_VFP_LOOP_END diff --git a/riscv/insns/vfwcvt_rtz_x_f_v.h b/riscv/insns/vfwcvt_rtz_x_f_v.h new file mode 100644 index 0000000..0afab8d --- /dev/null +++ b/riscv/insns/vfwcvt_rtz_x_f_v.h @@ -0,0 +1,11 @@ +// vfwcvt.x.f.v vd, vs2, vm +VI_CHECK_DSS(false); +if (P.VU.vsew == e32) + require(p->supports_extension('D')); + +VI_VFP_LOOP_BASE + softfloat_roundingMode = softfloat_round_minMag; + auto vs2 = P.VU.elt<float32_t>(rs2_num, i); + P.VU.elt<int64_t>(rd_num, i, true) = f32_to_i64(vs2, STATE.frm, true); + set_fp_exceptions; +VI_VFP_LOOP_WIDE_END diff --git a/riscv/insns/vfwcvt_rtz_xu_f_v.h b/riscv/insns/vfwcvt_rtz_xu_f_v.h new file mode 100644 index 0000000..d6bbc48 --- /dev/null +++ b/riscv/insns/vfwcvt_rtz_xu_f_v.h @@ -0,0 +1,11 @@ +// vfwcvt.xu.f.v vd, vs2, vm +VI_CHECK_DSS(false); +if (P.VU.vsew == e32) + require(p->supports_extension('D')); + +VI_VFP_LOOP_BASE + softfloat_roundingMode = softfloat_round_minMag; + auto vs2 = P.VU.elt<float32_t>(rs2_num, i); + P.VU.elt<uint64_t>(rd_num, i, true) = f32_to_ui64(vs2, STATE.frm, true); + set_fp_exceptions; +VI_VFP_LOOP_WIDE_END diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 252b196..757c734 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -511,6 +511,8 @@ riscv_insn_ext_v_alu_fp = \ vfclass_v \ vfcvt_f_x_v \ vfcvt_f_xu_v \ + vfcvt_rtz_x_f_v \ + vfcvt_rtz_xu_f_v \ vfcvt_x_f_v \ vfcvt_xu_f_v \ vfdiv_vf \ @@ -538,6 +540,8 @@ riscv_insn_ext_v_alu_fp = \ vfncvt_f_x_w \ vfncvt_f_xu_w \ vfncvt_rod_f_f_w \ + vfncvt_rtz_x_f_w \ + vfncvt_rtz_xu_f_w \ vfncvt_x_f_w \ vfncvt_xu_f_w \ vfnmacc_vf \ @@ -570,6 +574,8 @@ riscv_insn_ext_v_alu_fp = \ vfwcvt_f_f_v \ vfwcvt_f_x_v \ vfwcvt_f_xu_v \ + vfwcvt_rtz_x_f_v \ + vfwcvt_rtz_xu_f_v \ vfwcvt_x_f_v \ vfwcvt_xu_f_v \ vfwmacc_vf \ diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc index 3951af5..50f8b37 100644 --- a/spike_main/disasm.cc +++ b/spike_main/disasm.cc @@ -1055,9 +1055,15 @@ disassembler_t::disassembler_t(int xlen) add_insn(new disasm_insn_t(#name "cvt.f.x." #suf, \ match_##name##cvt_f_x_##suf, mask_##name##cvt_f_x_##suf, \ {&vd, &vs2, &opt, &vm})); \ + add_insn(new disasm_insn_t(#name "cvt.rtz.xu.f." #suf, \ + match_##name##cvt_xu_f_##suf, mask_##name##cvt_xu_f_##suf, \ + {&vd, &vs2, &opt, &vm})); \ + add_insn(new disasm_insn_t(#name "cvt.rtz.x.f." #suf, \ + match_##name##cvt_x_f_##suf, mask_##name##cvt_x_f_##suf, \ + {&vd, &vs2, &opt, &vm})); \ //OPFVV/OPFVF - //0b01_0000 + //0b00_0000 DISASM_OPIV_VF_INSN(vfadd); DISASM_OPIV_S__INSN(vfredsum); DISASM_OPIV_VF_INSN(vfsub); |