diff options
| -rw-r--r-- | riscv/csrs.cc | 1 | ||||
| -rw-r--r-- | riscv/execute.cc | 2 |
2 files changed, 1 insertions, 2 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 01720eb..b6ec20b 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -1354,7 +1354,6 @@ bool dcsr_csr_t::unlogged_write(const reg_t val) noexcept { ebreaku = proc->extension_enabled('U') ? get_field(val, DCSR_EBREAKU) : false; ebreakvs = proc->extension_enabled('H') ? get_field(val, CSR_DCSR_EBREAKVS) : false; ebreakvu = proc->extension_enabled('H') ? get_field(val, CSR_DCSR_EBREAKVU) : false; - halt = get_field(val, DCSR_NMIP); v = proc->extension_enabled('H') ? get_field(val, CSR_DCSR_V) : false; pelp = proc->extension_enabled(EXT_ZICFILP) ? static_cast<elp_t>(get_field(val, DCSR_PELP)) : elp_t::NO_LP_EXPECTED; diff --git a/riscv/execute.cc b/riscv/execute.cc index f263dce..cc77d88 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -216,7 +216,7 @@ void processor_t::step(size_t n) enter_debug_mode(DCSR_CAUSE_DEBUGINT); } else if (halt_request == HR_GROUP) { enter_debug_mode(DCSR_CAUSE_GROUP); - } // !!!The halt bit in DCSR is deprecated. + } else if (state.dcsr->halt) { enter_debug_mode(DCSR_CAUSE_HALT); } |