diff options
252 files changed, 249 insertions, 3 deletions
diff --git a/riscv/insns/vaadd_vi.h b/riscv/insns/vaadd_vi.h index bed1c38..17c4c93 100644 --- a/riscv/insns/vaadd_vi.h +++ b/riscv/insns/vaadd_vi.h @@ -8,3 +8,4 @@ VI_VI_LOOP vd = result; }) +VI_CHECK_1905 diff --git a/riscv/insns/vaadd_vv.h b/riscv/insns/vaadd_vv.h index b479970..f24d8cf 100644 --- a/riscv/insns/vaadd_vv.h +++ b/riscv/insns/vaadd_vv.h @@ -1,2 +1,3 @@ // vaadd.vv vd, vs2, vs1 VI_VVX_LOOP_AVG(vs1, +); +VI_CHECK_1905 diff --git a/riscv/insns/vaadd_vx.h b/riscv/insns/vaadd_vx.h index c811a0a..f41ad89 100644 --- a/riscv/insns/vaadd_vx.h +++ b/riscv/insns/vaadd_vx.h @@ -1,2 +1,3 @@ // vaadd.vx vd, vs2, rs1 VI_VVX_LOOP_AVG(rs1, +); +VI_CHECK_1905 diff --git a/riscv/insns/vadc_vi.h b/riscv/insns/vadc_vi.h index e481cfa..c5e8dd8 100644 --- a/riscv/insns/vadc_vi.h +++ b/riscv/insns/vadc_vi.h @@ -12,3 +12,4 @@ VI_VI_LOOP carry = (res >> sew) & 0x1u; v0 = (v0 & ~mmask) | ((carry << mpos) & mmask); }) +VI_CHECK_1905 diff --git a/riscv/insns/vadc_vv.h b/riscv/insns/vadc_vv.h index 1c5bd2b..2956e9e 100644 --- a/riscv/insns/vadc_vv.h +++ b/riscv/insns/vadc_vv.h @@ -12,3 +12,4 @@ VI_VV_LOOP carry = (res >> sew) & 0x1u; v0 = (v0 & ~mmask) | ((carry << mpos) & mmask); }) +VI_CHECK_1905 diff --git a/riscv/insns/vadc_vx.h b/riscv/insns/vadc_vx.h index 15819a7..94faa5d 100644 --- a/riscv/insns/vadc_vx.h +++ b/riscv/insns/vadc_vx.h @@ -12,3 +12,4 @@ VI_VX_LOOP carry = (res >> sew) & 0x1u; v0 = (v0 & ~mmask) | ((carry << mpos) & mmask); }) +VI_CHECK_1905 diff --git a/riscv/insns/vadd_vi.h b/riscv/insns/vadd_vi.h index d260809..44ff8a8 100644 --- a/riscv/insns/vadd_vi.h +++ b/riscv/insns/vadd_vi.h @@ -3,3 +3,4 @@ VI_VI_LOOP ({ vd = vsext(simm5 + vs2, sew); }) +VI_CHECK_1905 diff --git a/riscv/insns/vadd_vv.h b/riscv/insns/vadd_vv.h index 1ba12e6..69ebbad 100644 --- a/riscv/insns/vadd_vv.h +++ b/riscv/insns/vadd_vv.h @@ -3,3 +3,4 @@ VI_VV_LOOP ({ vd = vsext(vs1 + vs2, sew); }) +VI_CHECK_1905 diff --git a/riscv/insns/vadd_vx.h b/riscv/insns/vadd_vx.h index f420512..8bfcb86 100644 --- a/riscv/insns/vadd_vx.h +++ b/riscv/insns/vadd_vx.h @@ -3,3 +3,4 @@ VI_VX_LOOP ({ vd = vsext(rs1 + vs2, sew); }) +VI_CHECK_1905 diff --git a/riscv/insns/vand_vi.h b/riscv/insns/vand_vi.h index 84f90e1..53078e8 100644 --- a/riscv/insns/vand_vi.h +++ b/riscv/insns/vand_vi.h @@ -3,3 +3,4 @@ VI_VI_LOOP ({ vd = vsext(simm5 & vs2, sew); }) +VI_CHECK_1905 diff --git a/riscv/insns/vand_vv.h b/riscv/insns/vand_vv.h index dad16e1..d7a9c51 100644 --- a/riscv/insns/vand_vv.h +++ b/riscv/insns/vand_vv.h @@ -3,3 +3,4 @@ VI_VV_LOOP ({ vd = vsext(vs1 & vs2, sew); }) +VI_CHECK_1905 diff --git a/riscv/insns/vand_vx.h b/riscv/insns/vand_vx.h index a3294e4..6284346 100644 --- a/riscv/insns/vand_vx.h +++ b/riscv/insns/vand_vx.h @@ -3,3 +3,4 @@ VI_VX_LOOP ({ vd = vsext(rs1 & vs2, sew); }) +VI_CHECK_1905 diff --git a/riscv/insns/vasub_vv.h b/riscv/insns/vasub_vv.h index 5a5ccc9..ab6a10f 100644 --- a/riscv/insns/vasub_vv.h +++ b/riscv/insns/vasub_vv.h @@ -1,2 +1,3 @@ // vasub.vv vd, vs2, vs1 VI_VVX_LOOP_AVG(vs1, -); +VI_CHECK_1905 diff --git a/riscv/insns/vasub_vx.h b/riscv/insns/vasub_vx.h index c3cad4b..0fa98d5 100644 --- a/riscv/insns/vasub_vx.h +++ b/riscv/insns/vasub_vx.h @@ -1,2 +1,3 @@ // vasub.vx vd, vs2, rs1 VI_VVX_LOOP_AVG(rs1, -); +VI_CHECK_1905 diff --git a/riscv/insns/vcompress_vm.h b/riscv/insns/vcompress_vm.h index 0769486..6a4c6f4 100644 --- a/riscv/insns/vcompress_vm.h +++ b/riscv/insns/vcompress_vm.h @@ -49,3 +49,4 @@ for (reg_t i = pos ; i < P.VU.vlmax; ++i) { break; } } +VI_CHECK_1905 diff --git a/riscv/insns/vdiv_vv.h b/riscv/insns/vdiv_vv.h index 15b8a9c..52ffcba 100644 --- a/riscv/insns/vdiv_vv.h +++ b/riscv/insns/vdiv_vv.h @@ -3,3 +3,4 @@ VI_VV_LOOP ({ vd = vs2 / vs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vdiv_vx.h b/riscv/insns/vdiv_vx.h index f952db4..b66a598 100644 --- a/riscv/insns/vdiv_vx.h +++ b/riscv/insns/vdiv_vx.h @@ -3,3 +3,4 @@ VI_VX_LOOP ({ vd = vs2 / rs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vdivu_vv.h b/riscv/insns/vdivu_vv.h index 0b0f4b0..61af3a6 100644 --- a/riscv/insns/vdivu_vv.h +++ b/riscv/insns/vdivu_vv.h @@ -3,3 +3,4 @@ VI_VV_ULOOP ({ vd = vs2 / vs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vdivu_vx.h b/riscv/insns/vdivu_vx.h index bd0bd4c..eb3ee2c 100644 --- a/riscv/insns/vdivu_vx.h +++ b/riscv/insns/vdivu_vx.h @@ -3,3 +3,4 @@ VI_VX_ULOOP ({ vd = vs2 / rs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vdot_vv.h b/riscv/insns/vdot_vv.h index 7685230..d0403b1 100644 --- a/riscv/insns/vdot_vv.h +++ b/riscv/insns/vdot_vv.h @@ -3,3 +3,4 @@ VI_VV_LOOP ({ vd += vs2 * vs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vdotu_vv.h b/riscv/insns/vdotu_vv.h index 9c4c59d..c2cdcc9 100644 --- a/riscv/insns/vdotu_vv.h +++ b/riscv/insns/vdotu_vv.h @@ -3,3 +3,4 @@ VI_VV_ULOOP ({ vd += vs2 * vs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vfdot_vv.h b/riscv/insns/vfdot_vv.h index 8185b28..7539800 100644 --- a/riscv/insns/vfdot_vv.h +++ b/riscv/insns/vfdot_vv.h @@ -11,3 +11,4 @@ VFP_VV_LOOP softfloat_exceptionFlags = 1; }; }) +VI_CHECK_1905 diff --git a/riscv/insns/vfredmax_vs.h b/riscv/insns/vfredmax_vs.h index 63b235c..ca80cb8 100644 --- a/riscv/insns/vfredmax_vs.h +++ b/riscv/insns/vfredmax_vs.h @@ -3,3 +3,4 @@ VFP_VV_LOOP_REDUCTION ({ vd_0 = f32_max(vd_0, vs2); }) +VI_CHECK_1905 diff --git a/riscv/insns/vfredmin_vs.h b/riscv/insns/vfredmin_vs.h index eedc8e6..fcd3a32 100644 --- a/riscv/insns/vfredmin_vs.h +++ b/riscv/insns/vfredmin_vs.h @@ -3,3 +3,4 @@ VFP_VV_LOOP_REDUCTION ({ vd_0 = f32_min(vd_0, vs2); }) +VI_CHECK_1905 diff --git a/riscv/insns/vfredosum_vs.h b/riscv/insns/vfredosum_vs.h index a069c81..38d8cb0 100644 --- a/riscv/insns/vfredosum_vs.h +++ b/riscv/insns/vfredosum_vs.h @@ -3,3 +3,4 @@ VFP_VV_LOOP_REDUCTION ({ vd_0 = f32_add(vd_0, vs2); }) +VI_CHECK_1905 diff --git a/riscv/insns/vfredsum_vs.h b/riscv/insns/vfredsum_vs.h index 4d2ad2a..fe68396 100644 --- a/riscv/insns/vfredsum_vs.h +++ b/riscv/insns/vfredsum_vs.h @@ -3,3 +3,4 @@ VFP_VV_LOOP_REDUCTION ({ vd_0 = f32_add(vd_0, vs2); }) +VI_CHECK_1905 diff --git a/riscv/insns/vfunary0_vv.h b/riscv/insns/vfunary0_vv.h index 6c1254a..46843a9 100644 --- a/riscv/insns/vfunary0_vv.h +++ b/riscv/insns/vfunary0_vv.h @@ -88,3 +88,4 @@ VFP_VV_LOOP softfloat_exceptionFlags = 1; }; }) +VI_CHECK_1905 diff --git a/riscv/insns/vfwadd_vf.h b/riscv/insns/vfwadd_vf.h index b129fdf..d12453d 100644 --- a/riscv/insns/vfwadd_vf.h +++ b/riscv/insns/vfwadd_vf.h @@ -11,3 +11,4 @@ VFP_VF_LOOP softfloat_exceptionFlags = 1; }; }) +VI_CHECK_1905 diff --git a/riscv/insns/vfwadd_vv.h b/riscv/insns/vfwadd_vv.h index 53aad3a..e230067 100644 --- a/riscv/insns/vfwadd_vv.h +++ b/riscv/insns/vfwadd_vv.h @@ -11,3 +11,4 @@ VFP_VV_LOOP softfloat_exceptionFlags = 1; }; }) +VI_CHECK_1905 diff --git a/riscv/insns/vfwadd_wf.h b/riscv/insns/vfwadd_wf.h index 0c05fb3..e9b8061 100644 --- a/riscv/insns/vfwadd_wf.h +++ b/riscv/insns/vfwadd_wf.h @@ -12,3 +12,4 @@ VFP_VF_LOOP softfloat_exceptionFlags = 1; }; }) +VI_CHECK_1905 diff --git a/riscv/insns/vfwadd_wv.h b/riscv/insns/vfwadd_wv.h index 08b6724..1bdd9b9 100644 --- a/riscv/insns/vfwadd_wv.h +++ b/riscv/insns/vfwadd_wv.h @@ -12,3 +12,4 @@ VFP_VV_LOOP softfloat_exceptionFlags = 1; }; }) +VI_CHECK_1905 diff --git a/riscv/insns/vfwmacc_vf.h b/riscv/insns/vfwmacc_vf.h index 2ee400a..ff928e7 100644 --- a/riscv/insns/vfwmacc_vf.h +++ b/riscv/insns/vfwmacc_vf.h @@ -12,3 +12,4 @@ VFP_VVF_LOOP_WIDE break; }; }) +VI_CHECK_1905 diff --git a/riscv/insns/vfwmacc_vv.h b/riscv/insns/vfwmacc_vv.h index 3f07902..287a867 100644 --- a/riscv/insns/vfwmacc_vv.h +++ b/riscv/insns/vfwmacc_vv.h @@ -12,3 +12,4 @@ VFP_VVF_LOOP_WIDE break; }; }) +VI_CHECK_1905 diff --git a/riscv/insns/vfwmsac_vf.h b/riscv/insns/vfwmsac_vf.h index d12a8c2..8da3844 100644 --- a/riscv/insns/vfwmsac_vf.h +++ b/riscv/insns/vfwmsac_vf.h @@ -12,3 +12,4 @@ VFP_VVF_LOOP_WIDE break; }; }) +VI_CHECK_1905 diff --git a/riscv/insns/vfwmsac_vv.h b/riscv/insns/vfwmsac_vv.h index cd021d2..03dcaf9 100644 --- a/riscv/insns/vfwmsac_vv.h +++ b/riscv/insns/vfwmsac_vv.h @@ -12,3 +12,4 @@ VFP_VVF_LOOP_WIDE break; }; }) +VI_CHECK_1905 diff --git a/riscv/insns/vfwmul_vf.h b/riscv/insns/vfwmul_vf.h index f67bb1a..e33bc21 100644 --- a/riscv/insns/vfwmul_vf.h +++ b/riscv/insns/vfwmul_vf.h @@ -11,3 +11,4 @@ VFP_VVF_LOOP_WIDE softfloat_exceptionFlags = 1; }; }) +VI_CHECK_1905 diff --git a/riscv/insns/vfwmul_vv.h b/riscv/insns/vfwmul_vv.h index c3b3021..a6e68dd 100644 --- a/riscv/insns/vfwmul_vv.h +++ b/riscv/insns/vfwmul_vv.h @@ -11,3 +11,4 @@ VFP_VVF_LOOP_WIDE softfloat_exceptionFlags = 1; }; }) +VI_CHECK_1905 diff --git a/riscv/insns/vfwnmacc_vf.h b/riscv/insns/vfwnmacc_vf.h index bf7318f..9850209 100644 --- a/riscv/insns/vfwnmacc_vf.h +++ b/riscv/insns/vfwnmacc_vf.h @@ -12,3 +12,4 @@ VFP_VVF_LOOP_WIDE break; }; }) +VI_CHECK_1905 diff --git a/riscv/insns/vfwnmacc_vv.h b/riscv/insns/vfwnmacc_vv.h index bc9760b..ffdb5da 100644 --- a/riscv/insns/vfwnmacc_vv.h +++ b/riscv/insns/vfwnmacc_vv.h @@ -12,3 +12,4 @@ VFP_VVF_LOOP_WIDE break; }; }) +VI_CHECK_1905 diff --git a/riscv/insns/vfwnmsac_vf.h b/riscv/insns/vfwnmsac_vf.h index 16dc48c..e28af1d 100644 --- a/riscv/insns/vfwnmsac_vf.h +++ b/riscv/insns/vfwnmsac_vf.h @@ -13,3 +13,4 @@ VFP_VVF_LOOP_WIDE break; }; }) +VI_CHECK_1905 diff --git a/riscv/insns/vfwnmsac_vv.h b/riscv/insns/vfwnmsac_vv.h index 8d1df7f..d078476 100644 --- a/riscv/insns/vfwnmsac_vv.h +++ b/riscv/insns/vfwnmsac_vv.h @@ -13,3 +13,4 @@ VFP_VVF_LOOP_WIDE break; }; }) +VI_CHECK_1905 diff --git a/riscv/insns/vfwredosum_vs.h b/riscv/insns/vfwredosum_vs.h index 0fbdf79..1f8baa3 100644 --- a/riscv/insns/vfwredosum_vs.h +++ b/riscv/insns/vfwredosum_vs.h @@ -3,3 +3,4 @@ VFP_VV_LOOP_WIDE_REDUCTION ({ vd_0 = f64_add(vd_0, vs2); }) +VI_CHECK_1905 diff --git a/riscv/insns/vfwredsum_vs.h b/riscv/insns/vfwredsum_vs.h index fffefe5..9187344 100644 --- a/riscv/insns/vfwredsum_vs.h +++ b/riscv/insns/vfwredsum_vs.h @@ -3,3 +3,4 @@ VFP_VV_LOOP_WIDE_REDUCTION ({ vd_0 = f64_add(vd_0, vs2); }) +VI_CHECK_1905 diff --git a/riscv/insns/vfwsub_vf.h b/riscv/insns/vfwsub_vf.h index 2798f2b..fc6a9c4 100644 --- a/riscv/insns/vfwsub_vf.h +++ b/riscv/insns/vfwsub_vf.h @@ -11,3 +11,4 @@ VFP_VF_LOOP softfloat_exceptionFlags = 1; }; }) +VI_CHECK_1905 diff --git a/riscv/insns/vfwsub_vv.h b/riscv/insns/vfwsub_vv.h index fa0d326..b32a904 100644 --- a/riscv/insns/vfwsub_vv.h +++ b/riscv/insns/vfwsub_vv.h @@ -11,3 +11,4 @@ VFP_VV_LOOP softfloat_exceptionFlags = 1; }; }) +VI_CHECK_1905 diff --git a/riscv/insns/vfwsub_wf.h b/riscv/insns/vfwsub_wf.h index 1325b5c..43ab741 100644 --- a/riscv/insns/vfwsub_wf.h +++ b/riscv/insns/vfwsub_wf.h @@ -12,3 +12,4 @@ VFP_VF_LOOP softfloat_exceptionFlags = 1; }; }) +VI_CHECK_1905 diff --git a/riscv/insns/vfwsub_wv.h b/riscv/insns/vfwsub_wv.h index 8a0008e..6525cf4 100644 --- a/riscv/insns/vfwsub_wv.h +++ b/riscv/insns/vfwsub_wv.h @@ -12,3 +12,4 @@ VFP_VV_LOOP softfloat_exceptionFlags = 1; }; }) +VI_CHECK_1905 diff --git a/riscv/insns/vid_v.h b/riscv/insns/vid_v.h index bd30b8c..9f3acc3 100644 --- a/riscv/insns/vid_v.h +++ b/riscv/insns/vid_v.h @@ -26,3 +26,4 @@ for (reg_t i = 0 ; i < P.VU.vl; ++i) { break; } } +VI_CHECK_1905 diff --git a/riscv/insns/viota_m.h b/riscv/insns/viota_m.h index 7aae89a..cbf6130 100644 --- a/riscv/insns/viota_m.h +++ b/riscv/insns/viota_m.h @@ -49,3 +49,4 @@ for (reg_t i = 0 ; i < P.VU.vlmax; ++i) { if (has_one) cnt++; } +VI_CHECK_1905 diff --git a/riscv/insns/vlb_v.h b/riscv/insns/vlb_v.h index 7dbda80..531f2ec 100644 --- a/riscv/insns/vlb_v.h +++ b/riscv/insns/vlb_v.h @@ -39,3 +39,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlbff_v.h b/riscv/insns/vlbff_v.h index 0f565f0..1ec5ebe 100644 --- a/riscv/insns/vlbff_v.h +++ b/riscv/insns/vlbff_v.h @@ -50,3 +50,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlbu_v.h b/riscv/insns/vlbu_v.h index a1f462d..af3f9cd 100644 --- a/riscv/insns/vlbu_v.h +++ b/riscv/insns/vlbu_v.h @@ -39,3 +39,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlbuff_v.h b/riscv/insns/vlbuff_v.h index 7f624e2..b4a2702 100644 --- a/riscv/insns/vlbuff_v.h +++ b/riscv/insns/vlbuff_v.h @@ -50,3 +50,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vle_v.h b/riscv/insns/vle_v.h index 89752d1..64fae27 100644 --- a/riscv/insns/vle_v.h +++ b/riscv/insns/vle_v.h @@ -54,3 +54,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vleff_v.h b/riscv/insns/vleff_v.h index 3568a17..c89cbee 100644 --- a/riscv/insns/vleff_v.h +++ b/riscv/insns/vleff_v.h @@ -69,3 +69,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlh_v.h b/riscv/insns/vlh_v.h index ad96f70..f5750b9 100644 --- a/riscv/insns/vlh_v.h +++ b/riscv/insns/vlh_v.h @@ -36,3 +36,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlhff_v.h b/riscv/insns/vlhff_v.h index dec8afe..4c457ef 100644 --- a/riscv/insns/vlhff_v.h +++ b/riscv/insns/vlhff_v.h @@ -44,3 +44,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlhu_v.h b/riscv/insns/vlhu_v.h index e1f69b1..47c891e 100644 --- a/riscv/insns/vlhu_v.h +++ b/riscv/insns/vlhu_v.h @@ -35,3 +35,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlhuff_v.h b/riscv/insns/vlhuff_v.h index 4fee706..80f2399 100644 --- a/riscv/insns/vlhuff_v.h +++ b/riscv/insns/vlhuff_v.h @@ -44,3 +44,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlsb_v.h b/riscv/insns/vlsb_v.h index a8e7f25..6b92fc2 100644 --- a/riscv/insns/vlsb_v.h +++ b/riscv/insns/vlsb_v.h @@ -40,3 +40,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlsbu_v.h b/riscv/insns/vlsbu_v.h index ab15246..03939d3 100644 --- a/riscv/insns/vlsbu_v.h +++ b/riscv/insns/vlsbu_v.h @@ -40,3 +40,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlse_v.h b/riscv/insns/vlse_v.h index 458a6c4..d3608d2 100644 --- a/riscv/insns/vlse_v.h +++ b/riscv/insns/vlse_v.h @@ -55,3 +55,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlsh_v.h b/riscv/insns/vlsh_v.h index 7c63880..0759c74 100644 --- a/riscv/insns/vlsh_v.h +++ b/riscv/insns/vlsh_v.h @@ -36,3 +36,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlshu_v.h b/riscv/insns/vlshu_v.h index f4af25f..0b7869b 100644 --- a/riscv/insns/vlshu_v.h +++ b/riscv/insns/vlshu_v.h @@ -36,3 +36,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlsw_v.h b/riscv/insns/vlsw_v.h index 826cb0c..9b8b4aa 100644 --- a/riscv/insns/vlsw_v.h +++ b/riscv/insns/vlsw_v.h @@ -32,3 +32,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlswu_v.h b/riscv/insns/vlswu_v.h index 6708974..133dc42 100644 --- a/riscv/insns/vlswu_v.h +++ b/riscv/insns/vlswu_v.h @@ -32,3 +32,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlwff_v.h b/riscv/insns/vlwff_v.h index b2d35b4..4425e34 100644 --- a/riscv/insns/vlwff_v.h +++ b/riscv/insns/vlwff_v.h @@ -37,3 +37,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlwu_v.h b/riscv/insns/vlwu_v.h index 9fedd17..f8e51c7 100644 --- a/riscv/insns/vlwu_v.h +++ b/riscv/insns/vlwu_v.h @@ -31,3 +31,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlwuff_v.h b/riscv/insns/vlwuff_v.h index 70c76a4..edbff81 100644 --- a/riscv/insns/vlwuff_v.h +++ b/riscv/insns/vlwuff_v.h @@ -37,3 +37,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlxb_v.h b/riscv/insns/vlxb_v.h index 617b7f8..c12c024 100644 --- a/riscv/insns/vlxb_v.h +++ b/riscv/insns/vlxb_v.h @@ -49,3 +49,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlxbu_v.h b/riscv/insns/vlxbu_v.h index 8809f95..e5b3eb3 100644 --- a/riscv/insns/vlxbu_v.h +++ b/riscv/insns/vlxbu_v.h @@ -49,3 +49,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlxe_v.h b/riscv/insns/vlxe_v.h index 0bf92ff..3f6e4b6 100644 --- a/riscv/insns/vlxe_v.h +++ b/riscv/insns/vlxe_v.h @@ -60,3 +60,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlxh_v.h b/riscv/insns/vlxh_v.h index c9eaea1..500ded7 100644 --- a/riscv/insns/vlxh_v.h +++ b/riscv/insns/vlxh_v.h @@ -43,3 +43,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlxhu_v.h b/riscv/insns/vlxhu_v.h index ca0de31..1aa4e84 100644 --- a/riscv/insns/vlxhu_v.h +++ b/riscv/insns/vlxhu_v.h @@ -43,3 +43,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlxw_v.h b/riscv/insns/vlxw_v.h index 3c43746..5bb2d26 100644 --- a/riscv/insns/vlxw_v.h +++ b/riscv/insns/vlxw_v.h @@ -37,3 +37,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vlxwu_v.h b/riscv/insns/vlxwu_v.h index 4acf998..e50bf3d 100644 --- a/riscv/insns/vlxwu_v.h +++ b/riscv/insns/vlxwu_v.h @@ -37,3 +37,4 @@ if (vl != 0){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vmacc_vv.h b/riscv/insns/vmacc_vv.h index e6ec93f..ee33611 100644 --- a/riscv/insns/vmacc_vv.h +++ b/riscv/insns/vmacc_vv.h @@ -3,3 +3,4 @@ VI_VV_LOOP ({ vd = vs1 * vs2 + vd; }) +VI_CHECK_1905 diff --git a/riscv/insns/vmacc_vx.h b/riscv/insns/vmacc_vx.h index d40b264..b2bfffb 100644 --- a/riscv/insns/vmacc_vx.h +++ b/riscv/insns/vmacc_vx.h @@ -3,3 +3,4 @@ VI_VX_LOOP ({ vd = rs1 * vs2 + vd; }) +VI_CHECK_1905 diff --git a/riscv/insns/vmadd_vv.h b/riscv/insns/vmadd_vv.h index a1c0d2e..94c909c 100644 --- a/riscv/insns/vmadd_vv.h +++ b/riscv/insns/vmadd_vv.h @@ -3,3 +3,4 @@ VI_VV_LOOP ({ vd = vd * vs1 + vs2; }) +VI_CHECK_1905 diff --git a/riscv/insns/vmadd_vx.h b/riscv/insns/vmadd_vx.h index 1a8a001..08f3b6c 100644 --- a/riscv/insns/vmadd_vx.h +++ b/riscv/insns/vmadd_vx.h @@ -3,3 +3,4 @@ VI_VX_LOOP ({ vd = vd * rs1 + vs2; }) +VI_CHECK_1905 diff --git a/riscv/insns/vmax_vv.h b/riscv/insns/vmax_vv.h index f902370..4eed849 100644 --- a/riscv/insns/vmax_vv.h +++ b/riscv/insns/vmax_vv.h @@ -8,3 +8,4 @@ VI_VV_LOOP } }) +VI_CHECK_1905 diff --git a/riscv/insns/vmax_vx.h b/riscv/insns/vmax_vx.h index b223bfb..2ac7d55 100644 --- a/riscv/insns/vmax_vx.h +++ b/riscv/insns/vmax_vx.h @@ -8,3 +8,4 @@ VI_VX_LOOP } }) +VI_CHECK_1905 diff --git a/riscv/insns/vmaxu_vv.h b/riscv/insns/vmaxu_vv.h index 78d6246..ef5313b 100644 --- a/riscv/insns/vmaxu_vv.h +++ b/riscv/insns/vmaxu_vv.h @@ -7,3 +7,4 @@ VI_VV_ULOOP vd = vs2; } }) +VI_CHECK_1905 diff --git a/riscv/insns/vmaxu_vx.h b/riscv/insns/vmaxu_vx.h index 77d01d8..c711ee8 100644 --- a/riscv/insns/vmaxu_vx.h +++ b/riscv/insns/vmaxu_vx.h @@ -7,3 +7,4 @@ VI_VX_ULOOP vd = vs2; } }) +VI_CHECK_1905 diff --git a/riscv/insns/vmfirst_m.h b/riscv/insns/vmfirst_m.h index 47a34e1..9ca4549 100644 --- a/riscv/insns/vmfirst_m.h +++ b/riscv/insns/vmfirst_m.h @@ -20,3 +20,4 @@ for (reg_t i=p->VU.vstart; i<vl; ++i){ } p->VU.vstart = 0; WRITE_RD(pos); +VI_CHECK_1905 diff --git a/riscv/insns/vmin_vv.h b/riscv/insns/vmin_vv.h index 6a2ab35..97fe8e8 100644 --- a/riscv/insns/vmin_vv.h +++ b/riscv/insns/vmin_vv.h @@ -9,3 +9,4 @@ VI_VV_LOOP }) +VI_CHECK_1905 diff --git a/riscv/insns/vmin_vx.h b/riscv/insns/vmin_vx.h index 2428bcf..8804eed 100644 --- a/riscv/insns/vmin_vx.h +++ b/riscv/insns/vmin_vx.h @@ -9,3 +9,4 @@ VI_VX_LOOP }) +VI_CHECK_1905 diff --git a/riscv/insns/vminu_vv.h b/riscv/insns/vminu_vv.h index acd1eb0..3b1ac64 100644 --- a/riscv/insns/vminu_vv.h +++ b/riscv/insns/vminu_vv.h @@ -7,3 +7,4 @@ VI_VV_ULOOP vd = vs2; } }) +VI_CHECK_1905 diff --git a/riscv/insns/vminu_vx.h b/riscv/insns/vminu_vx.h index 3c15546..e474e83 100644 --- a/riscv/insns/vminu_vx.h +++ b/riscv/insns/vminu_vx.h @@ -8,3 +8,4 @@ VI_VX_ULOOP } }) +VI_CHECK_1905 diff --git a/riscv/insns/vmpopc_m.h b/riscv/insns/vmpopc_m.h index acd666e..af60dbc 100644 --- a/riscv/insns/vmpopc_m.h +++ b/riscv/insns/vmpopc_m.h @@ -22,3 +22,4 @@ for (reg_t i=p->VU.vstart; i<vl; ++i){ } p->VU.vstart = 0; WRITE_RD(popcount); +VI_CHECK_1905 diff --git a/riscv/insns/vmsac_vv.h b/riscv/insns/vmsac_vv.h index 7c10f29..6915892 100644 --- a/riscv/insns/vmsac_vv.h +++ b/riscv/insns/vmsac_vv.h @@ -3,3 +3,4 @@ VI_VV_LOOP ({ vd = -(vs1 * vs2) + vd; }) +VI_CHECK_1905 diff --git a/riscv/insns/vmsac_vx.h b/riscv/insns/vmsac_vx.h index 44920be..8d05a89 100644 --- a/riscv/insns/vmsac_vx.h +++ b/riscv/insns/vmsac_vx.h @@ -3,3 +3,4 @@ VI_VX_LOOP ({ vd = -(rs1 * vs2) + vd; }) +VI_CHECK_1905 diff --git a/riscv/insns/vmsbf_m.h b/riscv/insns/vmsbf_m.h index 6d9f6a0..0ca7150 100644 --- a/riscv/insns/vmsbf_m.h +++ b/riscv/insns/vmsbf_m.h @@ -29,3 +29,4 @@ for (reg_t i = 0 ; i < P.VU.vlmax; ++i) { vd = (vd & ~mmask) | ((res << mpos) & mmask); } } +VI_CHECK_1905 diff --git a/riscv/insns/vmsif_m.h b/riscv/insns/vmsif_m.h index 8edace9..5116d50 100644 --- a/riscv/insns/vmsif_m.h +++ b/riscv/insns/vmsif_m.h @@ -32,3 +32,4 @@ for (reg_t i = 0 ; i < P.VU.vlmax; ++i) { } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vmsof_m.h b/riscv/insns/vmsof_m.h index d0a0107..ba2cb90 100644 --- a/riscv/insns/vmsof_m.h +++ b/riscv/insns/vmsof_m.h @@ -28,3 +28,4 @@ for (reg_t i = 0 ; i < P.VU.vlmax; ++i) { vd = (vd & ~mmask) | ((res << mpos) & mmask); } } +VI_CHECK_1905 diff --git a/riscv/insns/vmsub_vv.h b/riscv/insns/vmsub_vv.h index 807f96a..ef06657 100644 --- a/riscv/insns/vmsub_vv.h +++ b/riscv/insns/vmsub_vv.h @@ -3,3 +3,4 @@ VI_VV_LOOP ({ vd = vd * vs1 - vs2; }) +VI_CHECK_1905 diff --git a/riscv/insns/vmsub_vx.h b/riscv/insns/vmsub_vx.h index 72f6b7d..c781824 100644 --- a/riscv/insns/vmsub_vx.h +++ b/riscv/insns/vmsub_vx.h @@ -3,3 +3,4 @@ VI_VX_LOOP ({ vd = (vd * rs1) - vs2; }) +VI_CHECK_1905 diff --git a/riscv/insns/vmul_vv.h b/riscv/insns/vmul_vv.h index a327817..da0b12f 100644 --- a/riscv/insns/vmul_vv.h +++ b/riscv/insns/vmul_vv.h @@ -3,3 +3,4 @@ VI_VV_LOOP ({ vd = vs2 * vs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vmul_vx.h b/riscv/insns/vmul_vx.h index 8d68390..1b1b5be 100644 --- a/riscv/insns/vmul_vx.h +++ b/riscv/insns/vmul_vx.h @@ -3,3 +3,4 @@ VI_VX_LOOP ({ vd = vs2 * rs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vmulh_vv.h b/riscv/insns/vmulh_vv.h index e861a33..a558433 100644 --- a/riscv/insns/vmulh_vv.h +++ b/riscv/insns/vmulh_vv.h @@ -3,3 +3,4 @@ VI_VV_LOOP ({ vd = ((int128_t)vs2 * vs1) >> sew; }) +VI_CHECK_1905 diff --git a/riscv/insns/vmulh_vx.h b/riscv/insns/vmulh_vx.h index b6b5503..f8eb54c 100644 --- a/riscv/insns/vmulh_vx.h +++ b/riscv/insns/vmulh_vx.h @@ -3,3 +3,4 @@ VI_VX_LOOP ({ vd = ((int128_t)vs2 * rs1) >> sew; }) +VI_CHECK_1905 diff --git a/riscv/insns/vmulhsu_vv.h b/riscv/insns/vmulhsu_vv.h index a932f02..65dcc98 100644 --- a/riscv/insns/vmulhsu_vv.h +++ b/riscv/insns/vmulhsu_vv.h @@ -35,3 +35,4 @@ VI_LOOP_BASE } } VI_LOOP_END +VI_CHECK_1905 diff --git a/riscv/insns/vmulhsu_vx.h b/riscv/insns/vmulhsu_vx.h index 56ab15f..9a8a134 100644 --- a/riscv/insns/vmulhsu_vx.h +++ b/riscv/insns/vmulhsu_vx.h @@ -35,3 +35,4 @@ VI_LOOP_BASE } } VI_LOOP_END +VI_CHECK_1905 diff --git a/riscv/insns/vmulhu_vv.h b/riscv/insns/vmulhu_vv.h index 8e318ed..0cac46f 100644 --- a/riscv/insns/vmulhu_vv.h +++ b/riscv/insns/vmulhu_vv.h @@ -3,3 +3,4 @@ VI_VV_ULOOP ({ vd = ((uint128_t)vs2 * vs1) >> sew; }) +VI_CHECK_1905 diff --git a/riscv/insns/vmulhu_vx.h b/riscv/insns/vmulhu_vx.h index 672ad32..096e0b2 100644 --- a/riscv/insns/vmulhu_vx.h +++ b/riscv/insns/vmulhu_vx.h @@ -3,3 +3,4 @@ VI_VX_ULOOP ({ vd = ((uint128_t)vs2 * rs1) >> sew; }) +VI_CHECK_1905 diff --git a/riscv/insns/vnclip_vi.h b/riscv/insns/vnclip_vi.h index 70ba915..01e95bc 100644 --- a/riscv/insns/vnclip_vi.h +++ b/riscv/insns/vnclip_vi.h @@ -20,3 +20,4 @@ VI_VI_LOOP } vd = result; }) +VI_CHECK_1905 diff --git a/riscv/insns/vnclip_vv.h b/riscv/insns/vnclip_vv.h index a5968c1..2076b39 100644 --- a/riscv/insns/vnclip_vv.h +++ b/riscv/insns/vnclip_vv.h @@ -32,3 +32,4 @@ VI_VVXI_LOOP_NARROW vd = result; }) +VI_CHECK_1905 diff --git a/riscv/insns/vnclip_vx.h b/riscv/insns/vnclip_vx.h index 00d7b2e..f96cc87 100644 --- a/riscv/insns/vnclip_vx.h +++ b/riscv/insns/vnclip_vx.h @@ -20,3 +20,4 @@ VI_VX_LOOP } vd = result; }) +VI_CHECK_1905 diff --git a/riscv/insns/vnclipu_vi.h b/riscv/insns/vnclipu_vi.h index ad593a1..f57fd14 100644 --- a/riscv/insns/vnclipu_vi.h +++ b/riscv/insns/vnclipu_vi.h @@ -18,3 +18,4 @@ VI_VVXI_LOOP_NARROW vd = result; }) +VI_CHECK_1905 diff --git a/riscv/insns/vnclipu_vv.h b/riscv/insns/vnclipu_vv.h index 8864f02..8c45f8a 100644 --- a/riscv/insns/vnclipu_vv.h +++ b/riscv/insns/vnclipu_vv.h @@ -23,3 +23,4 @@ VI_VVXI_LOOP_NARROW vd = result; }) +VI_CHECK_1905 diff --git a/riscv/insns/vnclipu_vx.h b/riscv/insns/vnclipu_vx.h index 4a5f2b4..582651a 100644 --- a/riscv/insns/vnclipu_vx.h +++ b/riscv/insns/vnclipu_vx.h @@ -23,3 +23,4 @@ VI_VVXI_LOOP_NARROW vd = result; }) +VI_CHECK_1905 diff --git a/riscv/insns/vnsra_vi.h b/riscv/insns/vnsra_vi.h index c0f9825..fb0d5ec 100644 --- a/riscv/insns/vnsra_vi.h +++ b/riscv/insns/vnsra_vi.h @@ -3,3 +3,4 @@ VI_VVXI_LOOP_NARROW ({ vd = vs2 >> (zimm5 & ((1u << log2(sew * 2)) - 1)); }) +VI_CHECK_1905 diff --git a/riscv/insns/vnsra_vv.h b/riscv/insns/vnsra_vv.h index 3ceaada..ecfaf03 100644 --- a/riscv/insns/vnsra_vv.h +++ b/riscv/insns/vnsra_vv.h @@ -3,3 +3,4 @@ VI_VVXI_LOOP_NARROW ({ vd = vs2 >> (vs1 & ((1u << log2(sew * 2)) - 1)); }) +VI_CHECK_1905 diff --git a/riscv/insns/vnsra_vx.h b/riscv/insns/vnsra_vx.h index e59baab..e6335ee 100644 --- a/riscv/insns/vnsra_vx.h +++ b/riscv/insns/vnsra_vx.h @@ -3,3 +3,4 @@ VI_VVXI_LOOP_NARROW ({ vd = vs2 >> (rs1 & ((1u << log2(sew * 2)) - 1)); }) +VI_CHECK_1905 diff --git a/riscv/insns/vnsrl_vi.h b/riscv/insns/vnsrl_vi.h index 58bea61..d83239e 100644 --- a/riscv/insns/vnsrl_vi.h +++ b/riscv/insns/vnsrl_vi.h @@ -3,3 +3,4 @@ VI_VVXI_LOOP_NARROW ({ vd = vs2_u >> (zimm5 & ((1u << log2(sew * 2)) - 1)); }) +VI_CHECK_1905 diff --git a/riscv/insns/vnsrl_vv.h b/riscv/insns/vnsrl_vv.h index 8a540e7..099c1a4 100644 --- a/riscv/insns/vnsrl_vv.h +++ b/riscv/insns/vnsrl_vv.h @@ -3,3 +3,4 @@ VI_VVXI_LOOP_NARROW ({ vd = vs2_u >> (vs1 & ((1u << log2(sew * 2)) - 1)); }) +VI_CHECK_1905 diff --git a/riscv/insns/vnsrl_vx.h b/riscv/insns/vnsrl_vx.h index 840eb34..82652ff 100644 --- a/riscv/insns/vnsrl_vx.h +++ b/riscv/insns/vnsrl_vx.h @@ -3,3 +3,4 @@ VI_VVXI_LOOP_NARROW ({ vd = vs2_u >> (rs1 & ((1u << log2(sew * 2)) - 1)); }) +VI_CHECK_1905 diff --git a/riscv/insns/vor_vi.h b/riscv/insns/vor_vi.h index 68a9cd8..3ee13b1 100644 --- a/riscv/insns/vor_vi.h +++ b/riscv/insns/vor_vi.h @@ -3,3 +3,4 @@ VI_VI_LOOP ({ vd = sext_xlen(simm5 | vs2); }) +VI_CHECK_1905 diff --git a/riscv/insns/vor_vv.h b/riscv/insns/vor_vv.h index 7777179..486ad87 100644 --- a/riscv/insns/vor_vv.h +++ b/riscv/insns/vor_vv.h @@ -3,3 +3,4 @@ VI_VV_LOOP ({ vd = sext_xlen(vs1 | vs2); }) +VI_CHECK_1905 diff --git a/riscv/insns/vor_vx.h b/riscv/insns/vor_vx.h index ab089ad..09abf59 100644 --- a/riscv/insns/vor_vx.h +++ b/riscv/insns/vor_vx.h @@ -3,3 +3,4 @@ VI_VX_LOOP ({ vd = vsext(rs1 | vs2, sew); }) +VI_CHECK_1905 diff --git a/riscv/insns/vredand_vs.h b/riscv/insns/vredand_vs.h index 6c2d908..22e5dfd 100644 --- a/riscv/insns/vredand_vs.h +++ b/riscv/insns/vredand_vs.h @@ -3,3 +3,4 @@ VI_VV_LOOP_REDUCTION ({ vd_0_res &= vs2; }) +VI_CHECK_1905 diff --git a/riscv/insns/vredmax_vs.h b/riscv/insns/vredmax_vs.h index be2e76a..8689744 100644 --- a/riscv/insns/vredmax_vs.h +++ b/riscv/insns/vredmax_vs.h @@ -3,3 +3,4 @@ VI_VV_LOOP_REDUCTION ({ vd_0_res = (vd_0_res >= vs2) ? vd_0_res : vs2; }) +VI_CHECK_1905 diff --git a/riscv/insns/vredmaxu_vs.h b/riscv/insns/vredmaxu_vs.h index 960f486..c281646 100644 --- a/riscv/insns/vredmaxu_vs.h +++ b/riscv/insns/vredmaxu_vs.h @@ -3,3 +3,4 @@ VI_VV_ULOOP_REDUCTION ({ vd_0_res = (vd_0_res >= vs2) ? vd_0_res : vs2; }) +VI_CHECK_1905 diff --git a/riscv/insns/vredmin_vs.h b/riscv/insns/vredmin_vs.h index 50359b7..a21644b 100644 --- a/riscv/insns/vredmin_vs.h +++ b/riscv/insns/vredmin_vs.h @@ -3,3 +3,4 @@ VI_VV_LOOP_REDUCTION ({ vd_0_res = (vd_0_res <= vs2) ? vd_0_res : vs2; }) +VI_CHECK_1905 diff --git a/riscv/insns/vredminu_vs.h b/riscv/insns/vredminu_vs.h index 7082475..40ff07a 100644 --- a/riscv/insns/vredminu_vs.h +++ b/riscv/insns/vredminu_vs.h @@ -3,3 +3,4 @@ VI_VV_ULOOP_REDUCTION ({ vd_0_res = (vd_0_res <= vs2) ? vd_0_res : vs2; }) +VI_CHECK_1905 diff --git a/riscv/insns/vredor_vs.h b/riscv/insns/vredor_vs.h index f7acd9a..ccd2981 100644 --- a/riscv/insns/vredor_vs.h +++ b/riscv/insns/vredor_vs.h @@ -3,3 +3,4 @@ VI_VV_LOOP_REDUCTION ({ vd_0_res |= vs2; }) +VI_CHECK_1905 diff --git a/riscv/insns/vredsum_vs.h b/riscv/insns/vredsum_vs.h index c4fefe5..3bca23a 100644 --- a/riscv/insns/vredsum_vs.h +++ b/riscv/insns/vredsum_vs.h @@ -3,3 +3,4 @@ VI_VV_LOOP_REDUCTION ({ vd_0_res += vs2; }) +VI_CHECK_1905 diff --git a/riscv/insns/vredxor_vs.h b/riscv/insns/vredxor_vs.h index bb81ad9..ad4b015 100644 --- a/riscv/insns/vredxor_vs.h +++ b/riscv/insns/vredxor_vs.h @@ -3,3 +3,4 @@ VI_VV_LOOP_REDUCTION ({ vd_0_res ^= vs2; }) +VI_CHECK_1905 diff --git a/riscv/insns/vrem_vv.h b/riscv/insns/vrem_vv.h index f7f5492..c580042 100644 --- a/riscv/insns/vrem_vv.h +++ b/riscv/insns/vrem_vv.h @@ -3,3 +3,4 @@ VI_VV_LOOP ({ vd = vs2 % vs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vrem_vx.h b/riscv/insns/vrem_vx.h index 1c0401e..717aa41 100644 --- a/riscv/insns/vrem_vx.h +++ b/riscv/insns/vrem_vx.h @@ -3,3 +3,4 @@ VI_VX_LOOP ({ vd = vs2 % rs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vremu_vv.h b/riscv/insns/vremu_vv.h index 914c562..708313e 100644 --- a/riscv/insns/vremu_vv.h +++ b/riscv/insns/vremu_vv.h @@ -3,3 +3,4 @@ VI_VV_ULOOP ({ vd = vs2 % vs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vremu_vx.h b/riscv/insns/vremu_vx.h index 69bc831..0ebc76e 100644 --- a/riscv/insns/vremu_vx.h +++ b/riscv/insns/vremu_vx.h @@ -3,3 +3,4 @@ VI_VX_LOOP ({ vd = vs2 % rs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vrgather_vi.h b/riscv/insns/vrgather_vi.h index c5c0f6d..2f9cf2c 100644 --- a/riscv/insns/vrgather_vi.h +++ b/riscv/insns/vrgather_vi.h @@ -41,3 +41,4 @@ for (reg_t i = vl; i < P.VU.vlmax; ++i) { break; } } +VI_CHECK_1905 diff --git a/riscv/insns/vrgather_vv.h b/riscv/insns/vrgather_vv.h index 854acb6..c6fbc11 100644 --- a/riscv/insns/vrgather_vv.h +++ b/riscv/insns/vrgather_vv.h @@ -49,3 +49,4 @@ for (reg_t i = vl; i < P.VU.vlmax; ++i) { break; } } +VI_CHECK_1905 diff --git a/riscv/insns/vrgather_vx.h b/riscv/insns/vrgather_vx.h index 85369f3..2b48b0c 100644 --- a/riscv/insns/vrgather_vx.h +++ b/riscv/insns/vrgather_vx.h @@ -42,3 +42,4 @@ for (reg_t i = vl; i < P.VU.vlmax; ++i) { break; } } +VI_CHECK_1905 diff --git a/riscv/insns/vrsub_vi.h b/riscv/insns/vrsub_vi.h index ae18c66..fb62057 100644 --- a/riscv/insns/vrsub_vi.h +++ b/riscv/insns/vrsub_vi.h @@ -3,3 +3,4 @@ VI_VI_LOOP ({ vd = vsext(simm5 - vs2, sew); }) +VI_CHECK_1905 diff --git a/riscv/insns/vrsub_vx.h b/riscv/insns/vrsub_vx.h index 8f8bc3b..afd4f37 100644 --- a/riscv/insns/vrsub_vx.h +++ b/riscv/insns/vrsub_vx.h @@ -3,3 +3,4 @@ VI_VX_LOOP ({ vd = vsext(rs1 - vs2, sew); }) +VI_CHECK_1905 diff --git a/riscv/insns/vsadd_vi.h b/riscv/insns/vsadd_vi.h index 73571fc..f6d0a25 100644 --- a/riscv/insns/vsadd_vi.h +++ b/riscv/insns/vsadd_vi.h @@ -25,3 +25,4 @@ VI_LOOP_BASE } P.VU.vxsat |= sat; VI_LOOP_END +VI_CHECK_1905 diff --git a/riscv/insns/vsadd_vv.h b/riscv/insns/vsadd_vv.h index 1cac976..e8f2497 100644 --- a/riscv/insns/vsadd_vv.h +++ b/riscv/insns/vsadd_vv.h @@ -26,3 +26,4 @@ VI_LOOP_BASE P.VU.vxsat |= sat; VI_LOOP_END +VI_CHECK_1905 diff --git a/riscv/insns/vsadd_vx.h b/riscv/insns/vsadd_vx.h index ed78253..f4ace47 100644 --- a/riscv/insns/vsadd_vx.h +++ b/riscv/insns/vsadd_vx.h @@ -25,3 +25,4 @@ VI_LOOP_BASE } P.VU.vxsat |= sat; VI_LOOP_END +VI_CHECK_1905 diff --git a/riscv/insns/vsaddu_vi.h b/riscv/insns/vsaddu_vi.h index ade91fe..c85ea3d 100644 --- a/riscv/insns/vsaddu_vi.h +++ b/riscv/insns/vsaddu_vi.h @@ -9,3 +9,4 @@ VI_VI_ULOOP p->VU.vxsat |= sat; }) +VI_CHECK_1905 diff --git a/riscv/insns/vsaddu_vv.h b/riscv/insns/vsaddu_vv.h index 9a2333e..cdf810a 100644 --- a/riscv/insns/vsaddu_vv.h +++ b/riscv/insns/vsaddu_vv.h @@ -9,3 +9,4 @@ VI_VV_ULOOP p->VU.vxsat |= sat; }) +VI_CHECK_1905 diff --git a/riscv/insns/vsaddu_vx.h b/riscv/insns/vsaddu_vx.h index 277e082..eba35bc 100644 --- a/riscv/insns/vsaddu_vx.h +++ b/riscv/insns/vsaddu_vx.h @@ -10,3 +10,4 @@ VI_VX_ULOOP p->VU.vxsat |= sat; }) +VI_CHECK_1905 diff --git a/riscv/insns/vsb_v.h b/riscv/insns/vsb_v.h index d9962a7..4eb09a8 100644 --- a/riscv/insns/vsb_v.h +++ b/riscv/insns/vsb_v.h @@ -28,3 +28,4 @@ for (reg_t i = p->VU.vstart; i < vl; ++i) { } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vsbc_vv.h b/riscv/insns/vsbc_vv.h index 400642b..a26a4d7 100644 --- a/riscv/insns/vsbc_vv.h +++ b/riscv/insns/vsbc_vv.h @@ -12,3 +12,4 @@ VI_VV_LOOP carry = (res >> sew) & 0x1u; v0 = (v0 & ~mmask) | ((carry << mpos) & mmask); }) +VI_CHECK_1905 diff --git a/riscv/insns/vsbc_vx.h b/riscv/insns/vsbc_vx.h index 0418296..cf7c509 100644 --- a/riscv/insns/vsbc_vx.h +++ b/riscv/insns/vsbc_vx.h @@ -12,3 +12,4 @@ VI_VX_LOOP carry = (res >> sew) & 0x1u; v0 = (v0 & ~mmask) | ((carry << mpos) & mmask); }) +VI_CHECK_1905 diff --git a/riscv/insns/vse_v.h b/riscv/insns/vse_v.h index c8895e2..2ef4d4e 100644 --- a/riscv/insns/vse_v.h +++ b/riscv/insns/vse_v.h @@ -32,3 +32,4 @@ for (reg_t i = p->VU.vstart; i < vl; ++i){ } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vseq_vi.h b/riscv/insns/vseq_vi.h index cfc1682..a348ae8 100644 --- a/riscv/insns/vseq_vi.h +++ b/riscv/insns/vseq_vi.h @@ -3,3 +3,4 @@ VI_VI_LOOP_CMP ({ res = simm5 == vs2; }) +VI_CHECK_1905 diff --git a/riscv/insns/vseq_vv.h b/riscv/insns/vseq_vv.h index 91fd204..5856d96 100644 --- a/riscv/insns/vseq_vv.h +++ b/riscv/insns/vseq_vv.h @@ -4,3 +4,4 @@ VI_VV_LOOP_CMP res = vs2 == vs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vseq_vx.h b/riscv/insns/vseq_vx.h index ab63323..951d9c8 100644 --- a/riscv/insns/vseq_vx.h +++ b/riscv/insns/vseq_vx.h @@ -3,3 +3,4 @@ VI_VX_LOOP_CMP ({ res = rs1 == vs2; }) +VI_CHECK_1905 diff --git a/riscv/insns/vsgt_vi.h b/riscv/insns/vsgt_vi.h index 4f7dea8..2986082 100644 --- a/riscv/insns/vsgt_vi.h +++ b/riscv/insns/vsgt_vi.h @@ -3,3 +3,4 @@ VI_VI_LOOP_CMP ({ res = vs2 > simm5; }) +VI_CHECK_1905 diff --git a/riscv/insns/vsgt_vx.h b/riscv/insns/vsgt_vx.h index 5f24db6..5c99f98 100644 --- a/riscv/insns/vsgt_vx.h +++ b/riscv/insns/vsgt_vx.h @@ -3,3 +3,4 @@ VI_VX_LOOP_CMP ({ res = vs2 > rs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vsgtu_vi.h b/riscv/insns/vsgtu_vi.h index 268d437..cef764e 100644 --- a/riscv/insns/vsgtu_vi.h +++ b/riscv/insns/vsgtu_vi.h @@ -3,3 +3,4 @@ VI_VI_ULOOP_CMP ({ res = vs2 > simm5; }) +VI_CHECK_1905 diff --git a/riscv/insns/vsgtu_vx.h b/riscv/insns/vsgtu_vx.h index 7f39800..03713e3 100644 --- a/riscv/insns/vsgtu_vx.h +++ b/riscv/insns/vsgtu_vx.h @@ -3,3 +3,4 @@ VI_VX_ULOOP_CMP ({ res = vs2 > rs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vsh_v.h b/riscv/insns/vsh_v.h index 4d95a9e..9949e5b 100644 --- a/riscv/insns/vsh_v.h +++ b/riscv/insns/vsh_v.h @@ -25,3 +25,4 @@ for (reg_t i = p->VU.vstart; i < vl; ++i) { } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vsle_vi.h b/riscv/insns/vsle_vi.h index f0f67d0..13546df 100644 --- a/riscv/insns/vsle_vi.h +++ b/riscv/insns/vsle_vi.h @@ -3,3 +3,4 @@ VI_VI_LOOP_CMP ({ res = vs2 <= simm5; }) +VI_CHECK_1905 diff --git a/riscv/insns/vsle_vv.h b/riscv/insns/vsle_vv.h index 30aba06..05d8273 100644 --- a/riscv/insns/vsle_vv.h +++ b/riscv/insns/vsle_vv.h @@ -3,3 +3,4 @@ VI_VV_LOOP_CMP ({ res = vs2 <= vs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vsle_vx.h b/riscv/insns/vsle_vx.h index c26d596..bce3ace 100644 --- a/riscv/insns/vsle_vx.h +++ b/riscv/insns/vsle_vx.h @@ -3,3 +3,4 @@ VI_VX_LOOP_CMP ({ res = vs2 <= rs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vsleu_vi.h b/riscv/insns/vsleu_vi.h index dc4fd18..9c8ef0b 100644 --- a/riscv/insns/vsleu_vi.h +++ b/riscv/insns/vsleu_vi.h @@ -3,3 +3,4 @@ VI_VI_ULOOP_CMP ({ res = vs2 <= simm5; }) +VI_CHECK_1905 diff --git a/riscv/insns/vsleu_vv.h b/riscv/insns/vsleu_vv.h index 0e46032..4cb19f4 100644 --- a/riscv/insns/vsleu_vv.h +++ b/riscv/insns/vsleu_vv.h @@ -3,3 +3,4 @@ VI_VV_ULOOP_CMP ({ res = vs2 <= vs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vsleu_vx.h b/riscv/insns/vsleu_vx.h index 935b176..aeecdf3 100644 --- a/riscv/insns/vsleu_vx.h +++ b/riscv/insns/vsleu_vx.h @@ -3,3 +3,4 @@ VI_VX_ULOOP_CMP ({ res = vs2 <= rs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vslide1down_vx.h b/riscv/insns/vslide1down_vx.h index 563e391..3f41633 100644 --- a/riscv/insns/vslide1down_vx.h +++ b/riscv/insns/vslide1down_vx.h @@ -26,4 +26,3 @@ VI_LOOP_BASE } } VI_LOOP_END - diff --git a/riscv/insns/vslide1up_vx.h b/riscv/insns/vslide1up_vx.h index d52a63e..b1a6585 100644 --- a/riscv/insns/vslide1up_vx.h +++ b/riscv/insns/vslide1up_vx.h @@ -26,3 +26,4 @@ VI_LOOP_BASE } } VI_LOOP_END +VI_CHECK_1905 diff --git a/riscv/insns/vslidedown_vi.h b/riscv/insns/vslidedown_vi.h index 5b0f7f3..846d393 100644 --- a/riscv/insns/vslidedown_vi.h +++ b/riscv/insns/vslidedown_vi.h @@ -18,4 +18,3 @@ VI_LOOP_BASE vd = vs2; } VI_LOOP_END - diff --git a/riscv/insns/vslidedown_vx.h b/riscv/insns/vslidedown_vx.h index d3ff2fd..7f5743a 100644 --- a/riscv/insns/vslidedown_vx.h +++ b/riscv/insns/vslidedown_vx.h @@ -17,4 +17,3 @@ VI_LOOP_BASE vd = vs2; } VI_LOOP_END - diff --git a/riscv/insns/vslideup_vi.h b/riscv/insns/vslideup_vi.h index efbc52f..64e3876 100644 --- a/riscv/insns/vslideup_vi.h +++ b/riscv/insns/vslideup_vi.h @@ -18,3 +18,4 @@ VI_LOOP_BASE vd = vs2; } VI_LOOP_END +VI_CHECK_1905 diff --git a/riscv/insns/vslideup_vx.h b/riscv/insns/vslideup_vx.h index 007eb20..7e1571e 100644 --- a/riscv/insns/vslideup_vx.h +++ b/riscv/insns/vslideup_vx.h @@ -18,3 +18,4 @@ VI_LOOP_BASE vd = vs2; } VI_LOOP_END +VI_CHECK_1905 diff --git a/riscv/insns/vsll_vi.h b/riscv/insns/vsll_vi.h index 5175285..78d836e 100644 --- a/riscv/insns/vsll_vi.h +++ b/riscv/insns/vsll_vi.h @@ -3,3 +3,4 @@ VI_VI_LOOP ({ vd = vs2 << (simm5 & ((1u << log2(sew)) - 1) & 0x1f); }) +VI_CHECK_1905 diff --git a/riscv/insns/vsll_vv.h b/riscv/insns/vsll_vv.h index 2fb7835..f0ea3b1 100644 --- a/riscv/insns/vsll_vv.h +++ b/riscv/insns/vsll_vv.h @@ -3,3 +3,4 @@ VI_VV_LOOP ({ vd = vsext(vs2 << (vs1 & (sew - 1)), sew); }) +VI_CHECK_1905 diff --git a/riscv/insns/vsll_vx.h b/riscv/insns/vsll_vx.h index abbb3d3..4eee248 100644 --- a/riscv/insns/vsll_vx.h +++ b/riscv/insns/vsll_vx.h @@ -3,3 +3,4 @@ VI_VX_LOOP ({ vd = vsext(vs2 << (rs1 & (sew-1)), sew); }) +VI_CHECK_1905 diff --git a/riscv/insns/vslt_vv.h b/riscv/insns/vslt_vv.h index 71e6f87..323a216 100644 --- a/riscv/insns/vslt_vv.h +++ b/riscv/insns/vslt_vv.h @@ -3,3 +3,4 @@ VI_VV_LOOP_CMP ({ res = vs2 < vs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vslt_vx.h b/riscv/insns/vslt_vx.h index b32bb14..7e96018 100644 --- a/riscv/insns/vslt_vx.h +++ b/riscv/insns/vslt_vx.h @@ -3,3 +3,4 @@ VI_VX_LOOP_CMP ({ res = vs2 < rs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vsltu_vv.h b/riscv/insns/vsltu_vv.h index 53a570a..4f403dc 100644 --- a/riscv/insns/vsltu_vv.h +++ b/riscv/insns/vsltu_vv.h @@ -3,3 +3,4 @@ VI_VV_ULOOP_CMP ({ res = vs2 < vs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vsltu_vx.h b/riscv/insns/vsltu_vx.h index 8082544..7d7e98a 100644 --- a/riscv/insns/vsltu_vx.h +++ b/riscv/insns/vsltu_vx.h @@ -3,3 +3,4 @@ VI_VX_ULOOP_CMP ({ res = vs2 < rs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vsmul_vv.h b/riscv/insns/vsmul_vv.h index 2f1e146..1ff9e8b 100644 --- a/riscv/insns/vsmul_vv.h +++ b/riscv/insns/vsmul_vv.h @@ -36,3 +36,4 @@ VI_VV_ULOOP } vd = result; }) +VI_CHECK_1905 diff --git a/riscv/insns/vsmul_vx.h b/riscv/insns/vsmul_vx.h index b32d732..e091259 100644 --- a/riscv/insns/vsmul_vx.h +++ b/riscv/insns/vsmul_vx.h @@ -37,3 +37,4 @@ VI_VX_ULOOP vd = result; }) +VI_CHECK_1905 diff --git a/riscv/insns/vsne_vi.h b/riscv/insns/vsne_vi.h index 5e9758e..c515c33 100644 --- a/riscv/insns/vsne_vi.h +++ b/riscv/insns/vsne_vi.h @@ -3,3 +3,4 @@ VI_VI_LOOP_CMP ({ res = vs2 != simm5; }) +VI_CHECK_1905 diff --git a/riscv/insns/vsne_vv.h b/riscv/insns/vsne_vv.h index e6a7174..b62bc50 100644 --- a/riscv/insns/vsne_vv.h +++ b/riscv/insns/vsne_vv.h @@ -3,3 +3,4 @@ VI_VV_LOOP_CMP ({ res = vs2 != vs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vsne_vx.h b/riscv/insns/vsne_vx.h index 9e4c155..6b5ba31 100644 --- a/riscv/insns/vsne_vx.h +++ b/riscv/insns/vsne_vx.h @@ -3,3 +3,4 @@ VI_VX_LOOP_CMP ({ res = vs2 != rs1; }) +VI_CHECK_1905 diff --git a/riscv/insns/vsra_vi.h b/riscv/insns/vsra_vi.h index adf20d5..ccc9681 100644 --- a/riscv/insns/vsra_vi.h +++ b/riscv/insns/vsra_vi.h @@ -3,3 +3,4 @@ VI_VI_LOOP ({ vd = vs2 >> (simm5 & ((1u << log2(sew)) - 1) & 0x1f); }) +VI_CHECK_1905 diff --git a/riscv/insns/vsra_vv.h b/riscv/insns/vsra_vv.h index e7e7302..3a23451 100644 --- a/riscv/insns/vsra_vv.h +++ b/riscv/insns/vsra_vv.h @@ -3,3 +3,4 @@ VI_VV_LOOP ({ vd = vs2 >> (vs1 & ((1u << log2(sew)) - 1)); }) +VI_CHECK_1905 diff --git a/riscv/insns/vsra_vx.h b/riscv/insns/vsra_vx.h index ddfd099..d5ad809 100644 --- a/riscv/insns/vsra_vx.h +++ b/riscv/insns/vsra_vx.h @@ -3,3 +3,4 @@ VI_VX_LOOP ({ vd = vs2 >> (rs1 & ((1u << log2(sew)) - 1)); }) +VI_CHECK_1905 diff --git a/riscv/insns/vsrl_vi.h b/riscv/insns/vsrl_vi.h index 4054a0b..8c875a6 100644 --- a/riscv/insns/vsrl_vi.h +++ b/riscv/insns/vsrl_vi.h @@ -3,3 +3,4 @@ VI_VI_ULOOP ({ vd = vs2 >> (simm5 & ((1u << log2(sew)) - 1) & 0x1f); }) +VI_CHECK_1905 diff --git a/riscv/insns/vsrl_vv.h b/riscv/insns/vsrl_vv.h index f50297d..a706213 100644 --- a/riscv/insns/vsrl_vv.h +++ b/riscv/insns/vsrl_vv.h @@ -3,3 +3,4 @@ VI_VV_ULOOP ({ vd = vs2 >> (vs1 & ((1u << log2(sew)) - 1)); }) +VI_CHECK_1905 diff --git a/riscv/insns/vsrl_vx.h b/riscv/insns/vsrl_vx.h index 838d879..3ebfe5c 100644 --- a/riscv/insns/vsrl_vx.h +++ b/riscv/insns/vsrl_vx.h @@ -3,3 +3,4 @@ VI_VX_ULOOP ({ vd = vs2 >> (rs1 & ((1u << log2(sew)) - 1)); }) +VI_CHECK_1905 diff --git a/riscv/insns/vssb_v.h b/riscv/insns/vssb_v.h index d5f49a0..ce5145d 100644 --- a/riscv/insns/vssb_v.h +++ b/riscv/insns/vssb_v.h @@ -30,3 +30,4 @@ for (reg_t i = p->VU.vstart; i < vl; ++i) { } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vsse_v.h b/riscv/insns/vsse_v.h index 08e77da..3ed5e12 100644 --- a/riscv/insns/vsse_v.h +++ b/riscv/insns/vsse_v.h @@ -33,3 +33,4 @@ for (reg_t i = p->VU.vstart; i < vl; ++i) { } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vssh_v.h b/riscv/insns/vssh_v.h index 426adcb..3a6575b 100644 --- a/riscv/insns/vssh_v.h +++ b/riscv/insns/vssh_v.h @@ -26,3 +26,4 @@ for (reg_t i = p->VU.vstart; i < vl; ++i) { } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vssra_vi.h b/riscv/insns/vssra_vi.h index 2819aa0..ba3205b 100644 --- a/riscv/insns/vssra_vi.h +++ b/riscv/insns/vssra_vi.h @@ -6,3 +6,4 @@ VI_VI_LOOP INT_ROUNDING(v2, xrm, sew); vd = v2 >> (simm5 & 0x1f); }) +VI_CHECK_1905 diff --git a/riscv/insns/vssra_vv.h b/riscv/insns/vssra_vv.h index feaf2f9..2029d52 100644 --- a/riscv/insns/vssra_vv.h +++ b/riscv/insns/vssra_vv.h @@ -6,3 +6,4 @@ VI_VV_LOOP INT_ROUNDING(v2, xrm, 1); vd = vsext(v2 >> (vs1 & ((2 * sew) - 1)), sew); }) +VI_CHECK_1905 diff --git a/riscv/insns/vssra_vx.h b/riscv/insns/vssra_vx.h index 4b74ce7..4d5ffcb 100644 --- a/riscv/insns/vssra_vx.h +++ b/riscv/insns/vssra_vx.h @@ -6,3 +6,4 @@ VI_VX_LOOP INT_ROUNDING(v2, xrm, sew); vd = vsext(v2 >> (rs1 & ((2 * sew) - 1)), sew); }) +VI_CHECK_1905 diff --git a/riscv/insns/vssrl_vi.h b/riscv/insns/vssrl_vi.h index 463700f..bf8f8e0 100644 --- a/riscv/insns/vssrl_vi.h +++ b/riscv/insns/vssrl_vi.h @@ -6,3 +6,4 @@ VI_VI_ULOOP INT_ROUNDING(v2, xrm, sew); vd = v2 >> (simm5 & 0x1f); }) +VI_CHECK_1905 diff --git a/riscv/insns/vssrl_vv.h b/riscv/insns/vssrl_vv.h index 7066f61..e359d51 100644 --- a/riscv/insns/vssrl_vv.h +++ b/riscv/insns/vssrl_vv.h @@ -6,3 +6,4 @@ VI_VV_ULOOP INT_ROUNDING(v2, xrm, 1); vd = vzext(v2 >> (vs1 & (2 * sew - 1)), sew); }) +VI_CHECK_1905 diff --git a/riscv/insns/vssrl_vx.h b/riscv/insns/vssrl_vx.h index 2a7bc84..a033d7b 100644 --- a/riscv/insns/vssrl_vx.h +++ b/riscv/insns/vssrl_vx.h @@ -6,3 +6,4 @@ VI_VX_ULOOP INT_ROUNDING(v2, xrm, sew); vd = v2 >> (rs1 & ((2 * sew) - 1)); }) +VI_CHECK_1905 diff --git a/riscv/insns/vssub_vv.h b/riscv/insns/vssub_vv.h index 6175acb..a1541bc 100644 --- a/riscv/insns/vssub_vv.h +++ b/riscv/insns/vssub_vv.h @@ -26,3 +26,4 @@ VI_LOOP_BASE } p->VU.vxsat |= sat; VI_LOOP_END +VI_CHECK_1905 diff --git a/riscv/insns/vssub_vx.h b/riscv/insns/vssub_vx.h index 709008a..fa5ccbe 100644 --- a/riscv/insns/vssub_vx.h +++ b/riscv/insns/vssub_vx.h @@ -26,3 +26,4 @@ VI_LOOP_BASE } p->VU.vxsat |= sat; VI_LOOP_END +VI_CHECK_1905 diff --git a/riscv/insns/vssubu_vv.h b/riscv/insns/vssubu_vv.h index a53f8e5..c744768 100644 --- a/riscv/insns/vssubu_vv.h +++ b/riscv/insns/vssubu_vv.h @@ -28,3 +28,4 @@ VI_LOOP_BASE p->VU.vxsat |= sat; VI_LOOP_END +VI_CHECK_1905 diff --git a/riscv/insns/vssubu_vx.h b/riscv/insns/vssubu_vx.h index 5304ec0..e89997a 100644 --- a/riscv/insns/vssubu_vx.h +++ b/riscv/insns/vssubu_vx.h @@ -26,3 +26,4 @@ VI_LOOP_BASE } p->VU.vxsat |= sat; VI_LOOP_END +VI_CHECK_1905 diff --git a/riscv/insns/vssw_v.h b/riscv/insns/vssw_v.h index 51201cf..1217175 100644 --- a/riscv/insns/vssw_v.h +++ b/riscv/insns/vssw_v.h @@ -23,3 +23,4 @@ for (reg_t i = p->VU.vstart; i < vl; ++i) { } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vsub_vv.h b/riscv/insns/vsub_vv.h index 7320ed0..38c35ef 100644 --- a/riscv/insns/vsub_vv.h +++ b/riscv/insns/vsub_vv.h @@ -3,3 +3,4 @@ VI_VV_LOOP ({ vd = vsext(vs2 - vs1, sew); }) +VI_CHECK_1905 diff --git a/riscv/insns/vsub_vx.h b/riscv/insns/vsub_vx.h index 009dcf0..cc8ca9a 100644 --- a/riscv/insns/vsub_vx.h +++ b/riscv/insns/vsub_vx.h @@ -3,3 +3,4 @@ VI_VX_LOOP ({ vd = vsext(vs2 - rs1, sew); }) +VI_CHECK_1905 diff --git a/riscv/insns/vsuxb_v.h b/riscv/insns/vsuxb_v.h index 33dfaf3..6ff9c53 100644 --- a/riscv/insns/vsuxb_v.h +++ b/riscv/insns/vsuxb_v.h @@ -32,3 +32,4 @@ for (reg_t i = p->VU.vstart; i < vl; ++i) { } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vsuxe_v.h b/riscv/insns/vsuxe_v.h index a2d6220..ef89f88 100644 --- a/riscv/insns/vsuxe_v.h +++ b/riscv/insns/vsuxe_v.h @@ -33,3 +33,4 @@ for (reg_t i = p->VU.vstart; i < vl; ++i) { } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vsuxh_v.h b/riscv/insns/vsuxh_v.h index 81fb9c7..6517528 100644 --- a/riscv/insns/vsuxh_v.h +++ b/riscv/insns/vsuxh_v.h @@ -27,3 +27,4 @@ for (reg_t i = p->VU.vstart; i < vl; ++i) { } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vsuxw_v.h b/riscv/insns/vsuxw_v.h index a850706..0889077 100644 --- a/riscv/insns/vsuxw_v.h +++ b/riscv/insns/vsuxw_v.h @@ -22,3 +22,4 @@ for (reg_t i = p->VU.vstart; i < vl; ++i) { } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vsxb_v.h b/riscv/insns/vsxb_v.h index 8da56c8..8eb1a3e 100644 --- a/riscv/insns/vsxb_v.h +++ b/riscv/insns/vsxb_v.h @@ -36,3 +36,4 @@ for (reg_t i = p->VU.vstart; i < vl; ++i) { } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vsxe_v.h b/riscv/insns/vsxe_v.h index d4dda67..8bc082d 100644 --- a/riscv/insns/vsxe_v.h +++ b/riscv/insns/vsxe_v.h @@ -38,3 +38,4 @@ for (reg_t i = p->VU.vstart; i < vl; ++i) { } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vsxh_v.h b/riscv/insns/vsxh_v.h index 7fbf9f0..0ac7d97 100644 --- a/riscv/insns/vsxh_v.h +++ b/riscv/insns/vsxh_v.h @@ -31,3 +31,4 @@ for (reg_t i = p->VU.vstart; i < vl; ++i) { } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vsxw_v.h b/riscv/insns/vsxw_v.h index 102df85..49673e3 100644 --- a/riscv/insns/vsxw_v.h +++ b/riscv/insns/vsxw_v.h @@ -26,3 +26,4 @@ for (reg_t i = p->VU.vstart; i < vl; ++i) { } } p->VU.vstart = 0; +VI_CHECK_1905 diff --git a/riscv/insns/vwadd_vv.h b/riscv/insns/vwadd_vv.h index da07886..8c39bbd 100644 --- a/riscv/insns/vwadd_vv.h +++ b/riscv/insns/vwadd_vv.h @@ -4,3 +4,4 @@ VI_VV_LOOP_WIDEN ({ V_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, +, +, int); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwadd_vx.h b/riscv/insns/vwadd_vx.h index d53ce4d..2e4aabf 100644 --- a/riscv/insns/vwadd_vx.h +++ b/riscv/insns/vwadd_vx.h @@ -4,3 +4,4 @@ VI_VX_LOOP_WIDEN ({ V_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, +, +, int); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwadd_wv.h b/riscv/insns/vwadd_wv.h index c0056ac..d6ea78e 100644 --- a/riscv/insns/vwadd_wv.h +++ b/riscv/insns/vwadd_wv.h @@ -4,3 +4,4 @@ VI_VV_LOOP_WIDEN ({ VI_WIDE_WVX_OP(vs1, +, int); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwadd_wx.h b/riscv/insns/vwadd_wx.h index fda0ba2..7934fbc 100644 --- a/riscv/insns/vwadd_wx.h +++ b/riscv/insns/vwadd_wx.h @@ -4,3 +4,4 @@ VI_VX_LOOP_WIDEN ({ VI_WIDE_WVX_OP(rs1, +, int); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwaddu_vv.h b/riscv/insns/vwaddu_vv.h index 63b3204..a6f0fbd 100644 --- a/riscv/insns/vwaddu_vv.h +++ b/riscv/insns/vwaddu_vv.h @@ -4,3 +4,4 @@ VI_VV_LOOP_WIDEN ({ V_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, +, +, uint); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwaddu_vx.h b/riscv/insns/vwaddu_vx.h index bd3cf49..db34018 100644 --- a/riscv/insns/vwaddu_vx.h +++ b/riscv/insns/vwaddu_vx.h @@ -4,3 +4,4 @@ VI_VX_LOOP_WIDEN ({ V_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, +, +, uint); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwaddu_wv.h b/riscv/insns/vwaddu_wv.h index 5f6869a..c27a3b0 100644 --- a/riscv/insns/vwaddu_wv.h +++ b/riscv/insns/vwaddu_wv.h @@ -4,3 +4,4 @@ VI_VV_LOOP_WIDEN ({ VI_WIDE_WVX_OP(vs1, +, uint); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwaddu_wx.h b/riscv/insns/vwaddu_wx.h index a3e62ea..f2f6839 100644 --- a/riscv/insns/vwaddu_wx.h +++ b/riscv/insns/vwaddu_wx.h @@ -4,3 +4,4 @@ VI_VX_LOOP_WIDEN ({ VI_WIDE_WVX_OP(rs1, +, uint); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwmacc_vv.h b/riscv/insns/vwmacc_vv.h index ca4f597..a111856 100644 --- a/riscv/insns/vwmacc_vv.h +++ b/riscv/insns/vwmacc_vv.h @@ -4,3 +4,4 @@ VI_VV_LOOP_WIDEN ({ V_WIDE_OP_AND_ASSIGN(vs2, vs1, vd_w, *, +, int); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwmacc_vx.h b/riscv/insns/vwmacc_vx.h index 312a9b1..3d1c463 100644 --- a/riscv/insns/vwmacc_vx.h +++ b/riscv/insns/vwmacc_vx.h @@ -4,3 +4,4 @@ VI_VX_LOOP_WIDEN ({ V_WIDE_OP_AND_ASSIGN(vs2, rs1, vd_w, *, +, int); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwmaccu_vv.h b/riscv/insns/vwmaccu_vv.h index 6503537..1365491 100644 --- a/riscv/insns/vwmaccu_vv.h +++ b/riscv/insns/vwmaccu_vv.h @@ -4,3 +4,4 @@ VI_VV_LOOP_WIDEN ({ V_WIDE_OP_AND_ASSIGN(vs2, vs1, vd_w, *, +, uint); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwmaccu_vx.h b/riscv/insns/vwmaccu_vx.h index 353299b..e0b29ee 100644 --- a/riscv/insns/vwmaccu_vx.h +++ b/riscv/insns/vwmaccu_vx.h @@ -4,3 +4,4 @@ VI_VX_LOOP_WIDEN ({ V_WIDE_OP_AND_ASSIGN(vs2, rs1, vd_w, *, +, uint); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwmsac_vv.h b/riscv/insns/vwmsac_vv.h index 9bbe596..e1c9986 100644 --- a/riscv/insns/vwmsac_vv.h +++ b/riscv/insns/vwmsac_vv.h @@ -4,3 +4,4 @@ VI_VV_LOOP_WIDEN ({ V_WIDE_OP_AND_ASSIGN(vs2, vs1, vd_w, *, -, int); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwmsac_vx.h b/riscv/insns/vwmsac_vx.h index 21d39fb..05ec105 100644 --- a/riscv/insns/vwmsac_vx.h +++ b/riscv/insns/vwmsac_vx.h @@ -4,3 +4,4 @@ VI_VX_LOOP_WIDEN ({ V_WIDE_OP_AND_ASSIGN(vs2, rs1, vd_w, *, -, int); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwmsacu_vv.h b/riscv/insns/vwmsacu_vv.h index 71162d6..f54446a 100644 --- a/riscv/insns/vwmsacu_vv.h +++ b/riscv/insns/vwmsacu_vv.h @@ -4,3 +4,4 @@ VI_VV_LOOP_WIDEN ({ V_WIDE_OP_AND_ASSIGN(vs2, vs1, vd_w, *, -, uint); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwmsacu_vx.h b/riscv/insns/vwmsacu_vx.h index e743f87..d4e1d8b 100644 --- a/riscv/insns/vwmsacu_vx.h +++ b/riscv/insns/vwmsacu_vx.h @@ -4,3 +4,4 @@ VI_VX_LOOP_WIDEN ({ V_WIDE_OP_AND_ASSIGN(vs2, rs1, vd_w, *, -, uint); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwmul_vv.h b/riscv/insns/vwmul_vv.h index ddd02bf..4628271 100644 --- a/riscv/insns/vwmul_vv.h +++ b/riscv/insns/vwmul_vv.h @@ -4,3 +4,4 @@ VI_VV_LOOP_WIDEN ({ V_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, *, +, int); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwmul_vx.h b/riscv/insns/vwmul_vx.h index 4eb01fa..8760a97 100644 --- a/riscv/insns/vwmul_vx.h +++ b/riscv/insns/vwmul_vx.h @@ -4,3 +4,4 @@ VI_VX_LOOP_WIDEN ({ V_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, *, +, int); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwmulsu_vv.h b/riscv/insns/vwmulsu_vv.h index a628314..62fecb3 100644 --- a/riscv/insns/vwmulsu_vv.h +++ b/riscv/insns/vwmulsu_vv.h @@ -14,3 +14,4 @@ VI_VV_LOOP_WIDEN break; } }) +VI_CHECK_1905 diff --git a/riscv/insns/vwmulsu_vx.h b/riscv/insns/vwmulsu_vx.h index 17598d4..290b90e 100644 --- a/riscv/insns/vwmulsu_vx.h +++ b/riscv/insns/vwmulsu_vx.h @@ -14,3 +14,4 @@ VI_VX_LOOP_WIDEN break; } }) +VI_CHECK_1905 diff --git a/riscv/insns/vwmulu_vv.h b/riscv/insns/vwmulu_vv.h index e9f696c..53a34c5 100644 --- a/riscv/insns/vwmulu_vv.h +++ b/riscv/insns/vwmulu_vv.h @@ -4,3 +4,4 @@ VI_VV_LOOP_WIDEN ({ V_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, *, +, uint); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwmulu_vx.h b/riscv/insns/vwmulu_vx.h index 0127221..1245809 100644 --- a/riscv/insns/vwmulu_vx.h +++ b/riscv/insns/vwmulu_vx.h @@ -4,3 +4,4 @@ VI_VX_LOOP_WIDEN ({ V_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, *, +, uint); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwredsum_vs.h b/riscv/insns/vwredsum_vs.h index fa557a1..189b810 100644 --- a/riscv/insns/vwredsum_vs.h +++ b/riscv/insns/vwredsum_vs.h @@ -3,3 +3,4 @@ VI_VV_LOOP_WIDE_REDUCTION ({ vd_0_res += vs2; }) +VI_CHECK_1905 diff --git a/riscv/insns/vwredsumu_vs.h b/riscv/insns/vwredsumu_vs.h index 3df343d..3ff50c2 100644 --- a/riscv/insns/vwredsumu_vs.h +++ b/riscv/insns/vwredsumu_vs.h @@ -3,3 +3,4 @@ VI_VV_ULOOP_WIDE_REDUCTION ({ vd_0_res += vs2; }) +VI_CHECK_1905 diff --git a/riscv/insns/vwsmacc_vv.h b/riscv/insns/vwsmacc_vv.h index e5e717f..1b188d9 100644 --- a/riscv/insns/vwsmacc_vv.h +++ b/riscv/insns/vwsmacc_vv.h @@ -1,2 +1,3 @@ // vwsmacc.vv vd, vs2, vs1 VI_VVX_LOOP_WIDE_SSMA(true, vs1); +VI_CHECK_1905 diff --git a/riscv/insns/vwsmacc_vx.h b/riscv/insns/vwsmacc_vx.h index 59d4e0a..4af83d4 100644 --- a/riscv/insns/vwsmacc_vx.h +++ b/riscv/insns/vwsmacc_vx.h @@ -1,2 +1,3 @@ // vwsmacc.vx vd, vs2, rs1 VI_VVX_LOOP_WIDE_SSMA(true, rs1); +VI_CHECK_1905 diff --git a/riscv/insns/vwsmaccu_vv.h b/riscv/insns/vwsmaccu_vv.h index 07d9af7..ad4f4aa 100644 --- a/riscv/insns/vwsmaccu_vv.h +++ b/riscv/insns/vwsmaccu_vv.h @@ -1,2 +1,3 @@ // vwsmaccu.vv vd, vs2, vs1 VI_VVX_LOOP_WIDE_USSMA(true, vs1); +VI_CHECK_1905 diff --git a/riscv/insns/vwsmaccu_vx.h b/riscv/insns/vwsmaccu_vx.h index 51b10ab..87b800a 100644 --- a/riscv/insns/vwsmaccu_vx.h +++ b/riscv/insns/vwsmaccu_vx.h @@ -1,2 +1,3 @@ // vwsmaccu vd, vs2, rs1 VI_VVX_LOOP_WIDE_USSMA(true, rs1); +VI_CHECK_1905 diff --git a/riscv/insns/vwsmsac_vv.h b/riscv/insns/vwsmsac_vv.h index 58bdcf5..b6d60b3 100644 --- a/riscv/insns/vwsmsac_vv.h +++ b/riscv/insns/vwsmsac_vv.h @@ -1,2 +1,3 @@ // vwsmsac.vv vd, vs2, vs1 VI_VVX_LOOP_WIDE_SSMA(false, vs1); +VI_CHECK_1905 diff --git a/riscv/insns/vwsmsac_vx.h b/riscv/insns/vwsmsac_vx.h index 49c8ca5..32b432a 100644 --- a/riscv/insns/vwsmsac_vx.h +++ b/riscv/insns/vwsmsac_vx.h @@ -1,2 +1,3 @@ // vwsmsac.vx vd, vs2, rs1 VI_VVX_LOOP_WIDE_SSMA(false, rs1); +VI_CHECK_1905 diff --git a/riscv/insns/vwsmsacu_vv.h b/riscv/insns/vwsmsacu_vv.h index 4406acc..6fa0720 100644 --- a/riscv/insns/vwsmsacu_vv.h +++ b/riscv/insns/vwsmsacu_vv.h @@ -1,2 +1,3 @@ // vwsmsacu vd, vs2, vs1 VI_VVX_LOOP_WIDE_USSMA(false, vs1); +VI_CHECK_1905 diff --git a/riscv/insns/vwsmsacu_vx.h b/riscv/insns/vwsmsacu_vx.h index a347aed..c22df9e 100644 --- a/riscv/insns/vwsmsacu_vx.h +++ b/riscv/insns/vwsmsacu_vx.h @@ -1,2 +1,3 @@ // vwsmsacu vd, vs2, rs1 VI_VVX_LOOP_WIDE_USSMA(false, rs1); +VI_CHECK_1905 diff --git a/riscv/insns/vwsub_vv.h b/riscv/insns/vwsub_vv.h index 897a414..d043912 100644 --- a/riscv/insns/vwsub_vv.h +++ b/riscv/insns/vwsub_vv.h @@ -4,3 +4,4 @@ VI_VV_LOOP_WIDEN ({ V_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, -, +, int); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwsub_vx.h b/riscv/insns/vwsub_vx.h index b49a13b..022fa38 100644 --- a/riscv/insns/vwsub_vx.h +++ b/riscv/insns/vwsub_vx.h @@ -4,3 +4,4 @@ VI_VX_LOOP_WIDEN ({ V_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, -, +, int); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwsub_wv.h b/riscv/insns/vwsub_wv.h index 62ce998..330d1f5 100644 --- a/riscv/insns/vwsub_wv.h +++ b/riscv/insns/vwsub_wv.h @@ -4,3 +4,4 @@ VI_VV_LOOP_WIDEN ({ VI_WIDE_WVX_OP(vs1, -, int); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwsub_wx.h b/riscv/insns/vwsub_wx.h index 426a9bf..e312508 100644 --- a/riscv/insns/vwsub_wx.h +++ b/riscv/insns/vwsub_wx.h @@ -4,3 +4,4 @@ VI_VX_LOOP_WIDEN ({ VI_WIDE_WVX_OP(rs1, -, int); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwsubu_vv.h b/riscv/insns/vwsubu_vv.h index 0abb718..633b430 100644 --- a/riscv/insns/vwsubu_vv.h +++ b/riscv/insns/vwsubu_vv.h @@ -4,3 +4,4 @@ VI_VV_LOOP_WIDEN ({ V_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, -, +, uint); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwsubu_vx.h b/riscv/insns/vwsubu_vx.h index 791a5ce..c3b8822 100644 --- a/riscv/insns/vwsubu_vx.h +++ b/riscv/insns/vwsubu_vx.h @@ -4,3 +4,4 @@ VI_VX_LOOP_WIDEN ({ V_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, -, +, uint); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwsubu_wv.h b/riscv/insns/vwsubu_wv.h index b86bff4..bd2d53c 100644 --- a/riscv/insns/vwsubu_wv.h +++ b/riscv/insns/vwsubu_wv.h @@ -4,3 +4,4 @@ VI_VV_LOOP_WIDEN ({ VI_WIDE_WVX_OP(vs1, -, uint); }) +VI_CHECK_1905 diff --git a/riscv/insns/vwsubu_wx.h b/riscv/insns/vwsubu_wx.h index c186e79..4daca0e 100644 --- a/riscv/insns/vwsubu_wx.h +++ b/riscv/insns/vwsubu_wx.h @@ -4,3 +4,4 @@ VI_VX_LOOP_WIDEN ({ VI_WIDE_WVX_OP(rs1, -, uint); }) +VI_CHECK_1905 diff --git a/riscv/insns/vxor_vi.h b/riscv/insns/vxor_vi.h index b6cffee..e4dfd08 100644 --- a/riscv/insns/vxor_vi.h +++ b/riscv/insns/vxor_vi.h @@ -3,3 +3,4 @@ VI_VI_LOOP ({ vd = sext_xlen(simm5 ^ vs2); }) +VI_CHECK_1905 diff --git a/riscv/insns/vxor_vv.h b/riscv/insns/vxor_vv.h index 78f7885..53b0371 100644 --- a/riscv/insns/vxor_vv.h +++ b/riscv/insns/vxor_vv.h @@ -3,3 +3,4 @@ VI_VV_LOOP ({ vd = sext_xlen(vs1 ^ vs2); }) +VI_CHECK_1905 diff --git a/riscv/insns/vxor_vx.h b/riscv/insns/vxor_vx.h index 427de78..56a1b8f 100644 --- a/riscv/insns/vxor_vx.h +++ b/riscv/insns/vxor_vx.h @@ -3,3 +3,4 @@ VI_VX_LOOP ({ vd = vsext(rs1 ^ vs2, sew); }) +VI_CHECK_1905 |