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-rw-r--r--riscv/decode.h8
-rw-r--r--riscv/processor.cc20
2 files changed, 13 insertions, 15 deletions
diff --git a/riscv/decode.h b/riscv/decode.h
index bf0d143..9c69b48 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -34,11 +34,11 @@ const int NCSR = 4096;
#define X_RA 1
#define X_SP 2
-#define VSR_VXRM_SHIFT 1
-#define VSR_VXRM (0x3 << VSR_VXRM_SHIFT)
+#define VCSR_VXRM_SHIFT 1
+#define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT)
-#define VSR_VXSAT_SHIFT 0
-#define VSR_VXSAT (0x1 << VSR_VXSAT_SHIFT)
+#define VCSR_VXSAT_SHIFT 0
+#define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT)
#define FP_RD_NE 0
#define FP_RD_0 1
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 8a94d81..efcbb2c 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -662,6 +662,11 @@ void processor_t::set_csr(int which, reg_t val)
state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
break;
+ case CSR_VCSR:
+ dirty_vs_state;
+ VU.vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
+ VU.vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
+ break;
case CSR_MSTATUS: {
if ((val ^ state.mstatus) &
(MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
@@ -870,11 +875,6 @@ void processor_t::set_csr(int which, reg_t val)
dirty_vs_state;
VU.vxrm = val & 0x3ul;
break;
- case CSR_VCSR :
- dirty_vs_state;
- VU.vxsat = (val & VSR_VXSAT) >> VSR_VXSAT_SHIFT;
- VU.vxrm = (val & VSR_VXRM) >> VSR_VXRM_SHIFT;
- break;
}
}
@@ -932,7 +932,10 @@ reg_t processor_t::get_csr(int which)
if (!supports_extension('F'))
break;
return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
-
+ case CSR_VCSR:
+ if (!supports_extension('V'))
+ break;
+ return (VU.vxsat << VCSR_VXSAT_SHIFT) | (VU.vxrm << VCSR_VXRM_SHIFT);
case CSR_INSTRET:
case CSR_CYCLE:
if (ctr_ok)
@@ -1091,11 +1094,6 @@ reg_t processor_t::get_csr(int which)
if (!supports_extension('V'))
break;
return VU.vlenb;
- case CSR_VCSR:
- require_vector_vs;
- if (!supports_extension('V'))
- break;
- return (VU.vxrm << VSR_VXRM_SHIFT) | (VU.vxsat << VSR_VXSAT_SHIFT);
}
throw trap_illegal_instruction(0);
}