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-rw-r--r--riscv/decode_macros.h2
-rw-r--r--riscv/insns/fcvt_bf16_s.h5
-rw-r--r--riscv/insns/fcvt_s_bf16.h5
-rw-r--r--riscv/riscv.mk.in12
4 files changed, 22 insertions, 2 deletions
diff --git a/riscv/decode_macros.h b/riscv/decode_macros.h
index 6bdd574..7ba132c 100644
--- a/riscv/decode_macros.h
+++ b/riscv/decode_macros.h
@@ -74,6 +74,7 @@ typedef unsigned __int128 uint128_t;
#define FRS2 READ_FREG(insn.rs2())
#define FRS3 READ_FREG(insn.rs3())
#define FRS1_H READ_FREG_H(insn.rs1())
+#define FRS1_BF FRS1_H
#define FRS1_F READ_FREG_F(insn.rs1())
#define FRS1_D READ_FREG_D(insn.rs1())
#define FRS2_H READ_FREG_H(insn.rs2())
@@ -95,6 +96,7 @@ do { \
WRITE_FRD(value); \
} \
} while (0)
+#define WRITE_FRD_BF WRITE_FRD_H
#define WRITE_FRD_F(value) \
do { \
if (p->extension_enabled(EXT_ZFINX)) \
diff --git a/riscv/insns/fcvt_bf16_s.h b/riscv/insns/fcvt_bf16_s.h
new file mode 100644
index 0000000..d625df8
--- /dev/null
+++ b/riscv/insns/fcvt_bf16_s.h
@@ -0,0 +1,5 @@
+require_extension(EXT_ZFBFMIN);
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD_BF(f32_to_bf16(FRS1_F));
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_bf16.h b/riscv/insns/fcvt_s_bf16.h
new file mode 100644
index 0000000..59a55cb
--- /dev/null
+++ b/riscv/insns/fcvt_s_bf16.h
@@ -0,0 +1,5 @@
+require_extension(EXT_ZFBFMIN);
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD_F(bf16_to_f32(FRS1_BF));
+set_fp_exceptions;
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 55fadc0..9e49c89 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -1356,8 +1356,15 @@ riscv_insn_ext_cmo = \
cbo_zero \
riscv_insn_ext_zicond = \
- czero_eqz \
- czero_nez \
+ czero_eqz \
+ czero_nez \
+
+riscv_insn_ext_zfbfmin = \
+ fcvt_bf16_s \
+ fcvt_s_bf16 \
+
+riscv_insn_ext_bf16 = \
+ $(riscv_insn_ext_zfbfmin) \
riscv_insn_list = \
$(riscv_insn_ext_a) \
@@ -1383,6 +1390,7 @@ riscv_insn_list = \
$(riscv_insn_smrnmi) \
$(riscv_insn_ext_cmo) \
$(riscv_insn_ext_zicond) \
+ $(riscv_insn_ext_bf16) \
riscv_gen_srcs = $(addsuffix .cc,$(riscv_insn_list))