diff options
| -rw-r--r-- | config.h.in | 3 | ||||
| -rwxr-xr-x | configure | 15 | ||||
| -rw-r--r-- | riscv/decode.h | 18 | ||||
| -rw-r--r-- | riscv/processor.cc | 6 | ||||
| -rw-r--r-- | riscv/riscv.ac | 5 | ||||
| -rw-r--r-- | riscv/trap.h | 2 |
6 files changed, 36 insertions, 13 deletions
diff --git a/config.h.in b/config.h.in index 6ef883d..fb0f56f 100644 --- a/config.h.in +++ b/config.h.in @@ -27,6 +27,9 @@ /* Define if floating-point instructions are supported */ #undef RISCV_ENABLE_FPU +/* Define if instruction compression is supported */ +#undef RISCV_ENABLE_RVC + /* Define if libopcodes exists */ #undef RISCV_HAVE_LIBOPCODES @@ -637,6 +637,7 @@ enable_stow enable_optional_subprojects enable_fpu enable_64bit +enable_rvc ' ac_precious_vars='build_alias host_alias @@ -1271,6 +1272,7 @@ Optional Features: Enable all optional subprojects --disable-fpu Disable floating-point --disable-64bit Disable 64-bit mode + --disable-rvc Disable instruction compression Some influential environment variables: CC C compiler command @@ -4045,6 +4047,19 @@ $as_echo "#define RISCV_ENABLE_64BIT /**/" >>confdefs.h fi +# Check whether --enable-rvc was given. +if test "${enable_rvc+set}" = set; then : + enableval=$enable_rvc; +fi + +if test "x$enable_rvc" != "xno"; then : + + +$as_echo "#define RISCV_ENABLE_RVC /**/" >>confdefs.h + + +fi + libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a as_ac_File=`$as_echo "ac_cv_file_$libopc" | $as_tr_sh` { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $libopc" >&5 diff --git a/riscv/decode.h b/riscv/decode.h index 8d96ab9..bb1f605 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -35,14 +35,14 @@ const int JUMP_ALIGN_BITS = 1; #define SR_ET 0x0000000000000001ULL #define SR_EF 0x0000000000000002ULL -#define SR_PS 0x0000000000000004ULL -#define SR_S 0x0000000000000008ULL -#define SR_UX 0x0000000000000010ULL -#define SR_SX 0x0000000000000020ULL -#define SR_UC 0x0000000000000040ULL -#define SR_SC 0x0000000000000080ULL +#define SR_EV 0x0000000000000004ULL +#define SR_EC 0x0000000000000008ULL +#define SR_PS 0x0000000000000010ULL +#define SR_S 0x0000000000000020ULL +#define SR_UX 0x0000000000000040ULL +#define SR_SX 0x0000000000000080ULL #define SR_IM 0x000000000000FF00ULL -#define SR_ZERO ~(SR_ET|SR_EF|SR_PS|SR_S|SR_UX|SR_SX|SR_UC|SR_SC|SR_IM) +#define SR_ZERO ~(SR_ET|SR_EF|SR_EV|SR_EC|SR_PS|SR_S|SR_UX|SR_SX|SR_IM) #define SR_IM_SHIFT 8 #define TIMER_IRQ 7 @@ -190,13 +190,13 @@ private: #define require_xpr64 if(!xpr64) throw trap_illegal_instruction #define require_xpr32 if(xpr64) throw trap_illegal_instruction #define require_fp if(!(sr & SR_EF)) throw trap_fp_disabled +#define require_vector if(!(sr & SR_EV)) throw trap_vector_disabled #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen)) #define set_fp_exceptions ({ set_fsr(fsr | \ (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \ softfloat_exceptionFlags = 0; }) -#define rvc_mode ((sr & SR_S) ? (sr & SR_SC) : (sr & SR_UC)) -#define require_rvc if(!rvc_mode) throw trap_illegal_instruction +#define require_rvc if(!(sr & SR_EC)) throw trap_illegal_instruction #define sext32(x) ((sreg_t)(int32_t)(x)) #define insn_length(x) (((x).bits & 0x3) < 0x3 ? 2 : 4) diff --git a/riscv/processor.cc b/riscv/processor.cc index 81ac42a..8aa2966 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -55,8 +55,8 @@ void processor_t::set_sr(uint32_t val) #ifndef RISCV_ENABLE_FPU sr &= ~SR_EF; #endif -#ifdef RISCV_ENABLE_RVC - sr &= ~SR_C; +#ifndef RISCV_ENABLE_RVC + sr &= ~SR_EC; #endif xprlen = ((sr & SR_S) ? (sr & SR_SX) : (sr & SR_UX)) ? 64 : 32; @@ -79,7 +79,7 @@ void processor_t::step(size_t n, bool noisy) if(interrupts && (sr & SR_ET)) take_trap(trap_interrupt,noisy); - insn_t insn = mmu.load_insn(pc, rvc_mode); + insn_t insn = mmu.load_insn(pc, sr & SR_EC); reg_t npc = pc + insn_length(insn); diff --git a/riscv/riscv.ac b/riscv/riscv.ac index 7898145..9bb4f2f 100644 --- a/riscv/riscv.ac +++ b/riscv/riscv.ac @@ -8,6 +8,11 @@ AS_IF([test "x$enable_64bit" != "xno"], [ AC_DEFINE([RISCV_ENABLE_64BIT],,[Define if 64-bit mode is supported]) ]) +AC_ARG_ENABLE([rvc], AS_HELP_STRING([--disable-rvc], [Disable instruction compression])) +AS_IF([test "x$enable_rvc" != "xno"], [ + AC_DEFINE([RISCV_ENABLE_RVC],,[Define if instruction compression is supported]) +]) + libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a AC_CHECK_FILES([$libopc],[have_libopcodes="yes"],[have_libopcodes="no"]) diff --git a/riscv/trap.h b/riscv/trap.h index 61b4436..a5c3212 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -13,7 +13,7 @@ DECLARE_TRAP(data_address_misaligned), \ DECLARE_TRAP(load_access_fault), \ DECLARE_TRAP(store_access_fault), \ - DECLARE_TRAP(reserved1), \ + DECLARE_TRAP(trap_vector_disabled), \ DECLARE_TRAP(reserved2), \ DECLARE_TRAP(reserved3), \ DECLARE_TRAP(reserved4), \ |