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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-21 19:46:38 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-21 20:45:57 -0700 |
| commit | 7eed9371f79f5c8f4675078d11a0228af9b5f571 (patch) | |
| tree | 07a0170c3ce8f301b5a79d690898997613a1664c /riscv | |
| parent | b2ae7abe22e0f0768b4c49d686a93f9c240985da (diff) | |
| download | spike-7eed9371f79f5c8f4675078d11a0228af9b5f571.zip spike-7eed9371f79f5c8f4675078d11a0228af9b5f571.tar.gz spike-7eed9371f79f5c8f4675078d11a0228af9b5f571.tar.bz2 | |
rvv: refine vl length and elemnet size checking
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/decode.h | 8 | ||||
| -rw-r--r-- | riscv/insns/vmsbf_m.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vmsif_m.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vmsof_m.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vmv_s_x.h | 3 |
5 files changed, 8 insertions, 9 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 1b844c0..55cbfbe 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -573,7 +573,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) // vector: loop header and end helper // #define VI_GENERAL_LOOP_BASE \ - require(P.VU.vsew == e8 || P.VU.vsew == e16 || P.VU.vsew == e32 || P.VU.vsew == e64); \ + require(P.VU.vsew >= e8 && P.VU.vsew <= e64); \ require_vector;\ reg_t vl = P.VU.vl; \ reg_t sew = P.VU.vsew; \ @@ -598,7 +598,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) P.VU.vstart = 0; #define VI_LOOP_CMP_BASE \ - require(P.VU.vsew == e8 || P.VU.vsew == e16 || P.VU.vsew == e32 || P.VU.vsew == e64); \ + require(P.VU.vsew >= e8 && P.VU.vsew <= e64); \ require_vector;\ reg_t vl = P.VU.vl; \ reg_t sew = P.VU.vsew; \ @@ -910,7 +910,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) // reduction loop - signed #define VI_LOOP_REDUCTION_BASE(x) \ - require(x == e8 || x == e16 || x == e32 || x == e64); \ + require(x >= e8 && x <= e64); \ reg_t vl = P.VU.vl; \ reg_t rd_num = insn.rd(); \ reg_t rs1_num = insn.rs1(); \ @@ -941,7 +941,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) // reduction loop - unsgied #define VI_ULOOP_REDUCTION_BASE(x) \ - require(x == e8 || x == e16 || x == e32 || x == e64); \ + require(x >= e8 && x <= e64); \ reg_t vl = P.VU.vl; \ reg_t rd_num = insn.rd(); \ reg_t rs1_num = insn.rs1(); \ diff --git a/riscv/insns/vmsbf_m.h b/riscv/insns/vmsbf_m.h index 11582e5..c7ec7f0 100644 --- a/riscv/insns/vmsbf_m.h +++ b/riscv/insns/vmsbf_m.h @@ -5,7 +5,7 @@ require(P.VU.vstart == 0); if (insn.v_vm() == 0) require(insn.rd() != 0 && insn.rd() != insn.rs2()); -reg_t vl = std::min(P.VU.vl, P.VU.VLEN); +reg_t vl = P.VU.vl; reg_t rd_num = insn.rd(); reg_t rs2_num = insn.rs2(); diff --git a/riscv/insns/vmsif_m.h b/riscv/insns/vmsif_m.h index e608a61..cda4313 100644 --- a/riscv/insns/vmsif_m.h +++ b/riscv/insns/vmsif_m.h @@ -5,7 +5,7 @@ require(P.VU.vstart == 0); if (insn.v_vm() == 0) require(insn.rd() != 0 && insn.rd() != insn.rs2()); -reg_t vl = std::min(P.VU.vl, P.VU.VLEN); +reg_t vl = P.VU.vl; reg_t rd_num = insn.rd(); reg_t rs2_num = insn.rs2(); diff --git a/riscv/insns/vmsof_m.h b/riscv/insns/vmsof_m.h index f6c65be..a84815b 100644 --- a/riscv/insns/vmsof_m.h +++ b/riscv/insns/vmsof_m.h @@ -5,7 +5,7 @@ require(P.VU.vstart == 0); if (insn.v_vm() == 0) require(insn.rd() != 0 && insn.rd() != insn.rs2()); -reg_t vl = std::min(P.VU.vl, P.VU.VLEN); +reg_t vl = P.VU.vl; reg_t rd_num = insn.rd(); reg_t rs2_num = insn.rs2(); diff --git a/riscv/insns/vmv_s_x.h b/riscv/insns/vmv_s_x.h index 9964901..74ab9e0 100644 --- a/riscv/insns/vmv_s_x.h +++ b/riscv/insns/vmv_s_x.h @@ -1,8 +1,7 @@ // vmv_s_x: vd[0] = rs1 require_vector; require(insn.v_vm() == 1); -require(P.VU.vsew == e8 || P.VU.vsew == e16 || - P.VU.vsew == e32 || P.VU.vsew == e64); +require(P.VU.vsew >= e8 && P.VU.vsew <= e64); reg_t vl = P.VU.vl; if (vl > 0 && P.VU.vstart < vl) { |