diff options
| author | Ryan Buchner <ryan.buchner@arilinc.com> | 2023-04-17 18:53:27 -0700 |
|---|---|---|
| committer | rbuchner <ryan.buchner@arilinc.com> | 2023-05-11 23:00:58 -0700 |
| commit | 3286d262eb42f414e7e43c734532f309dee9fe81 (patch) | |
| tree | 6d5dc02a01d222e803a733de32a622c855ccdfcb /riscv | |
| parent | dc3eb2d9e3b805ed1a1416c1e66584cf6520d0f1 (diff) | |
| download | spike-3286d262eb42f414e7e43c734532f309dee9fe81.zip spike-3286d262eb42f414e7e43c734532f309dee9fe81.tar.gz spike-3286d262eb42f414e7e43c734532f309dee9fe81.tar.bz2 | |
Rename RISCV_XLATE_VIRT to RISCV_XLATE_FORCED_VIRT
More readable/understandable.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/mmu.cc | 6 | ||||
| -rw-r--r-- | riscv/mmu.h | 8 |
2 files changed, 7 insertions, 7 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index be24f40..f6f0a0d 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -66,7 +66,7 @@ reg_t mmu_t::translate(reg_t addr, reg_t len, access_type type, uint32_t xlate_f if (get_field(proc->state.mstatus->read(), MSTATUS_MPV) && mode != PRV_M) virt = true; } - if (xlate_flags & RISCV_XLATE_VIRT) { + if (xlate_flags & RISCV_XLATE_FORCED_VIRT) { virt = true; mode = get_field(proc->state.hstatus->read(), HSTATUS_SPVP); } @@ -236,7 +236,7 @@ void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes, uint32_t xlate if ((addr & (len - 1)) == 0) { load_slow_path_intrapage(addr, len, bytes, xlate_flags); } else { - bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_VIRT & xlate_flags); + bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_FORCED_VIRT & xlate_flags); if (!is_misaligned_enabled()) throw trap_load_address_misaligned(gva, addr, 0, 0); @@ -284,7 +284,7 @@ void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes, uint32_ check_triggers(triggers::OPERATION_STORE, addr, reg_from_bytes(len, bytes)); if (addr & (len - 1)) { - bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_VIRT & xlate_flags); + bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_FORCED_VIRT & xlate_flags); if (!is_misaligned_enabled()) throw trap_store_address_misaligned(gva, addr, 0, 0); diff --git a/riscv/mmu.h b/riscv/mmu.h index ef054cf..d63a43f 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -51,7 +51,7 @@ public: mmu_t(simif_t* sim, endianness_t endianness, processor_t* proc); ~mmu_t(); -#define RISCV_XLATE_VIRT (1U << 0) +#define RISCV_XLATE_FORCED_VIRT (1U << 0) #define RISCV_XLATE_VIRT_HLVX (1U << 1) #define RISCV_XLATE_LR (1U << 2) @@ -81,12 +81,12 @@ public: template<typename T> T guest_load(reg_t addr) { - return load<T>(addr, RISCV_XLATE_VIRT); + return load<T>(addr, RISCV_XLATE_FORCED_VIRT); } template<typename T> T guest_load_x(reg_t addr) { - return load<T>(addr, RISCV_XLATE_VIRT|RISCV_XLATE_VIRT_HLVX); + return load<T>(addr, RISCV_XLATE_FORCED_VIRT|RISCV_XLATE_VIRT_HLVX); } template<typename T> @@ -108,7 +108,7 @@ public: template<typename T> void guest_store(reg_t addr, T val) { - store(addr, val, RISCV_XLATE_VIRT); + store(addr, val, RISCV_XLATE_FORCED_VIRT); } // AMO/Zicbom faults should be reported as store faults |