From 3286d262eb42f414e7e43c734532f309dee9fe81 Mon Sep 17 00:00:00 2001 From: Ryan Buchner Date: Mon, 17 Apr 2023 18:53:27 -0700 Subject: Rename RISCV_XLATE_VIRT to RISCV_XLATE_FORCED_VIRT More readable/understandable. --- riscv/mmu.cc | 6 +++--- riscv/mmu.h | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) (limited to 'riscv') diff --git a/riscv/mmu.cc b/riscv/mmu.cc index be24f40..f6f0a0d 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -66,7 +66,7 @@ reg_t mmu_t::translate(reg_t addr, reg_t len, access_type type, uint32_t xlate_f if (get_field(proc->state.mstatus->read(), MSTATUS_MPV) && mode != PRV_M) virt = true; } - if (xlate_flags & RISCV_XLATE_VIRT) { + if (xlate_flags & RISCV_XLATE_FORCED_VIRT) { virt = true; mode = get_field(proc->state.hstatus->read(), HSTATUS_SPVP); } @@ -236,7 +236,7 @@ void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes, uint32_t xlate if ((addr & (len - 1)) == 0) { load_slow_path_intrapage(addr, len, bytes, xlate_flags); } else { - bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_VIRT & xlate_flags); + bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_FORCED_VIRT & xlate_flags); if (!is_misaligned_enabled()) throw trap_load_address_misaligned(gva, addr, 0, 0); @@ -284,7 +284,7 @@ void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes, uint32_ check_triggers(triggers::OPERATION_STORE, addr, reg_from_bytes(len, bytes)); if (addr & (len - 1)) { - bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_VIRT & xlate_flags); + bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_FORCED_VIRT & xlate_flags); if (!is_misaligned_enabled()) throw trap_store_address_misaligned(gva, addr, 0, 0); diff --git a/riscv/mmu.h b/riscv/mmu.h index ef054cf..d63a43f 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -51,7 +51,7 @@ public: mmu_t(simif_t* sim, endianness_t endianness, processor_t* proc); ~mmu_t(); -#define RISCV_XLATE_VIRT (1U << 0) +#define RISCV_XLATE_FORCED_VIRT (1U << 0) #define RISCV_XLATE_VIRT_HLVX (1U << 1) #define RISCV_XLATE_LR (1U << 2) @@ -81,12 +81,12 @@ public: template T guest_load(reg_t addr) { - return load(addr, RISCV_XLATE_VIRT); + return load(addr, RISCV_XLATE_FORCED_VIRT); } template T guest_load_x(reg_t addr) { - return load(addr, RISCV_XLATE_VIRT|RISCV_XLATE_VIRT_HLVX); + return load(addr, RISCV_XLATE_FORCED_VIRT|RISCV_XLATE_VIRT_HLVX); } template @@ -108,7 +108,7 @@ public: template void guest_store(reg_t addr, T val) { - store(addr, val, RISCV_XLATE_VIRT); + store(addr, val, RISCV_XLATE_FORCED_VIRT); } // AMO/Zicbom faults should be reported as store faults -- cgit v1.1