diff options
| author | Andrew Waterman <andrew@sifive.com> | 2022-03-28 14:56:36 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-03-30 01:41:17 -0700 |
| commit | 1e159e462720f043b0c2ff9c0cd2541fed88f1a9 (patch) | |
| tree | 56f3251c9fec423e6e3cc9fa7856b8b400837888 /riscv/sim.cc | |
| parent | 3bbaab01762f0b5bac1fd816370c270ffe28fd6b (diff) | |
| download | spike-1e159e462720f043b0c2ff9c0cd2541fed88f1a9.zip spike-1e159e462720f043b0c2ff9c0cd2541fed88f1a9.tar.gz spike-1e159e462720f043b0c2ff9c0cd2541fed88f1a9.tar.bz2 | |
Implement Sv57 and Sv57x4 translation modes
Diffstat (limited to 'riscv/sim.cc')
| -rw-r--r-- | riscv/sim.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index f3999a7..0831582 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -153,6 +153,8 @@ sim_t::sim_t(const cfg_t *cfg, const char* varch, bool halted, bool real_time_cl procs[cpu_idx]->set_mmu_capability(IMPL_MMU_SV39); } else if (strncmp(mmu_type, "riscv,sv48", strlen("riscv,sv48")) == 0) { procs[cpu_idx]->set_mmu_capability(IMPL_MMU_SV48); + } else if (strncmp(mmu_type, "riscv,sv57", strlen("riscv,sv57")) == 0) { + procs[cpu_idx]->set_mmu_capability(IMPL_MMU_SV57); } else if (strncmp(mmu_type, "riscv,sbare", strlen("riscv,sbare")) == 0) { //has been set in the beginning } else { |