From 1e159e462720f043b0c2ff9c0cd2541fed88f1a9 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 28 Mar 2022 14:56:36 -0700 Subject: Implement Sv57 and Sv57x4 translation modes --- riscv/sim.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'riscv/sim.cc') diff --git a/riscv/sim.cc b/riscv/sim.cc index f3999a7..0831582 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -153,6 +153,8 @@ sim_t::sim_t(const cfg_t *cfg, const char* varch, bool halted, bool real_time_cl procs[cpu_idx]->set_mmu_capability(IMPL_MMU_SV39); } else if (strncmp(mmu_type, "riscv,sv48", strlen("riscv,sv48")) == 0) { procs[cpu_idx]->set_mmu_capability(IMPL_MMU_SV48); + } else if (strncmp(mmu_type, "riscv,sv57", strlen("riscv,sv57")) == 0) { + procs[cpu_idx]->set_mmu_capability(IMPL_MMU_SV57); } else if (strncmp(mmu_type, "riscv,sbare", strlen("riscv,sbare")) == 0) { //has been set in the beginning } else { -- cgit v1.1