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| author | Andrew Waterman <andrew@sifive.com> | 2023-02-05 16:02:30 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-02-05 16:02:30 -0800 |
| commit | 456c9e19d811ddc5da99974a40ee79a6f535a597 (patch) | |
| tree | 3bd813365ea097bdee34d25871f4e1bf6e76ac48 /riscv/sim.cc | |
| parent | e85f86695092f1377a515c94de5c706bcff1f2bd (diff) | |
| download | spike-plic-clint-endian.zip spike-plic-clint-endian.tar.gz spike-plic-clint-endian.tar.bz2 | |
Make clint tolerant of discontiguous hart IDsplic-clint-endian
Diffstat (limited to 'riscv/sim.cc')
| -rw-r--r-- | riscv/sim.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 4e5e9a7..114151a 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -116,7 +116,7 @@ sim_t::sim_t(const cfg_t *cfg, bool halted, // setting the dtb_file argument has one. reg_t clint_base; if (fdt_parse_clint(fdt, &clint_base, "riscv,clint0") == 0) { - clint.reset(new clint_t(procs, CPU_HZ / INSNS_PER_RTC_TICK, cfg->real_time_clint())); + clint.reset(new clint_t(this, CPU_HZ / INSNS_PER_RTC_TICK, cfg->real_time_clint())); bus.add_device(clint_base, clint.get()); } |