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author | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
commit | 68aeeb5500521ff52c216862f9a653b64191f3ad (patch) | |
tree | 407230ff48f79f177a792451598d9b2b6e3d34a0 /riscv/riscv.mk.in | |
parent | 191634d2854dfed448fc323195f9b65c305e2d77 (diff) | |
parent | 03be4ae6c7b8e9865083b61427ff9724c7706fcf (diff) | |
download | spike-plic_uart_v1.zip spike-plic_uart_v1.tar.gz spike-plic_uart_v1.tar.bz2 |
Merge branch 'master' into plic_uart_v1plic_uart_v1
Diffstat (limited to 'riscv/riscv.mk.in')
-rw-r--r-- | riscv/riscv.mk.in | 35 |
1 files changed, 34 insertions, 1 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 708cead..91f7a5f 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -3,8 +3,14 @@ get_opcode = $(shell grep ^DECLARE_INSN.*\\\<$(2)\\\> $(1) | sed 's/DECLARE_INSN riscv_subproject_deps = \ fdt \ + disasm \ + fesvr \ softfloat \ +riscv_CFLAGS = -fPIC + +riscv_install_shared_lib = yes + riscv_install_prog_srcs = \ riscv_hdrs = \ @@ -13,9 +19,12 @@ riscv_hdrs = \ decode.h \ devices.h \ dts.h \ + isa_parser.h \ mmu.h \ cfg.h \ processor.h \ + p_ext_macros.h \ + v_ext_macros.h \ sim.h \ simif.h \ trap.h \ @@ -34,7 +43,31 @@ riscv_hdrs = \ csrs.h \ triggers.h \ -riscv_install_hdrs = mmio_plugin.h +riscv_install_hdrs = \ + abstract_device.h \ + cachesim.h \ + cfg.h \ + common.h \ + csrs.h \ + debug_module.h \ + debug_rom_defines.h \ + decode.h \ + devices.h \ + encoding.h \ + entropy_source.h \ + isa_parser.h \ + log_file.h \ + memtracer.h \ + mmio_plugin.h \ + mmu.h \ + p_ext_macros.h \ + platform.h \ + processor.h \ + sim.h \ + simif.h \ + trap.h \ + triggers.h \ + v_ext_macros.h \ riscv_precompiled_hdrs = \ insn_template.h \ |