From a59c44eb468ae366dbf2dc60c371b1c090e311cf Mon Sep 17 00:00:00 2001 From: Pirmin Vogel Date: Mon, 16 May 2022 12:10:09 +0200 Subject: Include recently added headers in riscv/riscv.mk.in --- riscv/riscv.mk.in | 3 +++ 1 file changed, 3 insertions(+) (limited to 'riscv/riscv.mk.in') diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 0c6b977..45fe2eb 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -13,9 +13,12 @@ riscv_hdrs = \ decode.h \ devices.h \ dts.h \ + isa_parser.h \ mmu.h \ cfg.h \ processor.h \ + p_ext_macros.h \ + v_ext_macros.h \ sim.h \ simif.h \ trap.h \ -- cgit v1.1 From 204a639780dda374320a4ef31d714694db7ae46f Mon Sep 17 00:00:00 2001 From: Jerin Joy Date: Fri, 23 Sep 2022 15:43:32 -0700 Subject: Build and install lib and header dependencies for Hammer https://github.com/rivosinc/hammer Signed-off-by: Jerin Joy --- riscv/riscv.mk.in | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) (limited to 'riscv/riscv.mk.in') diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 45fe2eb..bbac794 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -3,8 +3,14 @@ get_opcode = $(shell grep ^DECLARE_INSN.*\\\<$(2)\\\> $(1) | sed 's/DECLARE_INSN riscv_subproject_deps = \ fdt \ + disasm \ + fesvr \ softfloat \ +riscv_CFLAGS = -fPIC + +riscv_install_shared_lib = yes + riscv_install_prog_srcs = \ riscv_hdrs = \ @@ -37,7 +43,31 @@ riscv_hdrs = \ csrs.h \ triggers.h \ -riscv_install_hdrs = mmio_plugin.h +riscv_install_hdrs = \ + abstract_device.h \ + cachesim.h \ + cfg.h \ + common.h \ + csrs.h \ + debug_module.h \ + debug_rom_defines.h \ + decode.h \ + devices.h \ + encoding.h \ + entropy_source.h \ + isa_parser.h \ + log_file.h \ + memtracer.h \ + mmio_plugin.h \ + mmu.h \ + p_ext_macros.h \ + platform.h \ + processor.h \ + sim.h \ + simif.h \ + trap.h \ + triggers.h \ + v_ext_macros.h \ riscv_precompiled_hdrs = \ insn_template.h \ -- cgit v1.1