rvv: remove tail-zero

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

19 files changed, 46 insertions, 185 deletions

diff --git a/configure b/configure
index ceb28af..7253082 100755
--- a/configure
+++ b/configure
@@ -1362,7 +1362,7 @@ Optional Packages:
   --with-PACKAGE[=ARG]    use PACKAGE [ARG=yes]
   --without-PACKAGE       do not use PACKAGE (same as --with-PACKAGE=no)
   --with-isa=RV64IMAFDC   Sets the default RISC-V ISA
-  --with-varch=v128:e32:s128:t0
+  --with-varch=v128:e32:s128
                           Sets the default vector config
 
 Some influential environment variables:
@@ -4632,7 +4632,7 @@ _ACEOF
 else
 
 cat >>confdefs.h <<_ACEOF
-#define DEFAULT_VARCH "v128:e32:s128:t0"
+#define DEFAULT_VARCH "v128:e32:s128"
 _ACEOF
 
 fi
diff --git a/riscv/decode.h b/riscv/decode.h
index 95ba44f..f2ccf83 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -68,23 +68,6 @@ const int NCSR = 4096;
 #define MAX_INSN_LENGTH 8
 #define PC_ALIGN 2
 
-#ifdef WORDS_BIGENDIAN
-  // Elements are stored in opposite order, see comment in processor.h
-  #define TAIL_ZERO(x) \
-    uint8_t *tail = &P.VU.elt<uint8_t>(rd_num, vl * (x) - 1); \
-    memset(tail - (P.VU.vlmax - vl) * (x), 0, (P.VU.vlmax - vl) * (x));
-  #define TAIL_ZERO_REDUCTION(x) \
-    uint8_t *tail = (uint8_t *)&P.VU.elt<type_sew_t<x>::type>(rd_num, 0); \
-    memset(tail - ((P.VU.get_vlen() - x) >> 3), 0, (P.VU.get_vlen() - x) >> 3);
-#else
-  #define TAIL_ZERO(x) \
-    uint8_t *tail = &P.VU.elt<uint8_t>(rd_num, vl * (x)); \
-    memset(tail, 0, (P.VU.vlmax - vl) * (x));
-  #define TAIL_ZERO_REDUCTION(x) \
-    uint8_t *tail = (uint8_t *)&P.VU.elt<type_sew_t<x>::type>(rd_num, 1); \
-    memset(tail, 0, (P.VU.get_vlen() - x) >> 3);
-#endif
-
 typedef uint64_t insn_bits_t;
 class insn_t
 {
@@ -386,9 +369,7 @@ extern bool g_vector_mistrap;
   }
 
 #define VI_ELEMENT_SKIP(inx) \
-  if (inx >= vl && P.VU.TZ) { \
-    is_valid = false; \
-  } else if (inx >= vl && !P.VU.TZ) { \
+  if (inx >= vl) { \
     continue; \
   } else if (inx < P.VU.vstart) { \
     continue; \
@@ -500,48 +481,22 @@ static inline bool is_overlaped(const int astart, const int asize,
   reg_t rs2_num = insn.rs2(); \
   for (reg_t i=P.VU.vstart; i<vl; ++i){ 
 
-#define VI_TAIL_ZERO(elm) \
-  if (vl != 0 && vl < P.VU.vlmax && P.VU.TZ) { \
-    TAIL_ZERO((sew >> 3) * elm); \
-  }
-
-#define VI_TAIL_ZERO_MASK(dst) \
-  if (vl != 0 && P.VU.TZ){ \
-    for (reg_t i=vl; i<P.VU.vlmax; ++i){ \
-      const int mlen = P.VU.vmlen; \
-      const int midx = (mlen * i) / 64; \
-      const int mpos = (mlen * i) % 64; \
-      uint64_t mmask = (UINT64_MAX << (64 - mlen)) >> (64 - mlen - mpos); \
-      uint64_t &vdi = P.VU.elt<uint64_t>(dst, midx); \
-      vdi = (vdi & ~mmask);\
-    }\
-  }\
-
 #define VI_LOOP_BASE \
     VI_GENERAL_LOOP_BASE \
     VI_LOOP_ELEMENT_SKIP();
 
 #define VI_LOOP_END \
   } \
-  VI_TAIL_ZERO(1) \
-  P.VU.vstart = 0;
-
-#define VI_LOOP_END_NO_TAIL_ZERO \
-  } \
   P.VU.vstart = 0;
 
 #define VI_LOOP_WIDEN_END \
   } \
-  VI_TAIL_ZERO(2); \
   P.VU.vstart = 0;
 
 #define VI_LOOP_REDUCTION_END(x) \
   } \
   if (vl > 0) { \
     vd_0_des = vd_0_res; \
-    if (P.VU.TZ) { \
-      TAIL_ZERO_REDUCTION(x); \
-    } \
   } \
   P.VU.vstart = 0; 
 
@@ -562,7 +517,6 @@ static inline bool is_overlaped(const int astart, const int asize,
 #define VI_LOOP_CMP_END \
     vdi = (vdi & ~mmask) | (((res) << mpos) & mmask); \
   } \
-  VI_TAIL_ZERO_MASK(rd_num); \
   P.VU.vstart = 0;
 
 #define VI_LOOP_MASK(op) \
@@ -578,17 +532,6 @@ static inline bool is_overlaped(const int astart, const int asize,
     uint64_t &res = P.VU.elt<uint64_t>(insn.rd(), midx); \
     res = (res & ~mmask) | ((op) & (1ULL << mpos)); \
   } \
-  \
-  if (P.VU.TZ) {\
-  for (reg_t i = vl; i < P.VU.vlmax && i > 0; ++i) { \
-    int mlen = P.VU.vmlen; \
-    int midx = (mlen * i) / 64; \
-    int mpos = (mlen * i) % 64; \
-    uint64_t mmask = (UINT64_MAX << (64 - mlen)) >> (64 - mlen - mpos); \
-    uint64_t &res = P.VU.elt<uint64_t>(insn.rd(), midx); \
-    res = (res & ~mmask); \
-    } \
-  } \
   P.VU.vstart = 0;
 
 #define VI_LOOP_NSHIFT_BASE \
@@ -1375,7 +1318,6 @@ VI_LOOP_END
       BODY; \
     } \
   } \
-  VI_TAIL_ZERO_MASK(rd_num);
 
 #define VI_XI_LOOP_CARRY(BODY) \
   VI_CHECK_MSS(false); \
@@ -1394,7 +1336,6 @@ VI_LOOP_END
       BODY; \
     } \
   } \
-  VI_TAIL_ZERO_MASK(rd_num);
 
 // average loop
 #define VI_VVX_LOOP_AVG(opd, op, is_vs1) \
@@ -1480,11 +1421,8 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
   const reg_t vlmax = P.VU.vlmax; \
   const reg_t vlmul = P.VU.vlmul; \
   for (reg_t i = 0; i < vlmax && vl != 0; ++i) { \
-    bool is_valid = true; \
     VI_STRIP(i) \
     VI_ELEMENT_SKIP(i); \
-    if (!is_valid) \
-      continue; \
     for (reg_t fn = 0; fn < nf; ++fn) { \
       st_width##_t val = 0; \
       switch (P.VU.vsew) { \
@@ -1516,11 +1454,10 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
   const reg_t vlmax = P.VU.vlmax; \
   const reg_t vlmul = P.VU.vlmul; \
   for (reg_t i = 0; i < vlmax && vl != 0; ++i) { \
-    bool is_valid = true; \
     VI_ELEMENT_SKIP(i); \
     VI_STRIP(i); \
     for (reg_t fn = 0; fn < nf; ++fn) { \
-      ld_width##_t val = is_valid ? MMU.load_##ld_width(baseAddr + (stride) + (offset) * elt_byte) : 0; \
+      ld_width##_t val = MMU.load_##ld_width(baseAddr + (stride) + (offset) * elt_byte); \
       if (vd + fn >= NVPR){ \
          P.VU.vstart = vreg_inx;\
          require(false); \
@@ -1556,7 +1493,6 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
   const reg_t vlmax = P.VU.vlmax; \
   const reg_t vlmul = P.VU.vlmul; \
   for (reg_t i = 0; i < vlmax && vl != 0; ++i) { \
-    bool is_valid = true; \
     VI_STRIP(i); \
     VI_ELEMENT_SKIP(i); \
     \
@@ -1565,20 +1501,20 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
       \
       switch (sew) { \
       case e8: \
-        p->VU.elt<uint8_t>(rd_num + fn * vlmul, vreg_inx) = is_valid ? val : 0; \
+        p->VU.elt<uint8_t>(rd_num + fn * vlmul, vreg_inx) = val; \
         break; \
       case e16: \
-        p->VU.elt<uint16_t>(rd_num + fn * vlmul, vreg_inx) = is_valid ? val : 0; \
+        p->VU.elt<uint16_t>(rd_num + fn * vlmul, vreg_inx) = val; \
         break; \
       case e32: \
-        p->VU.elt<uint32_t>(rd_num + fn * vlmul, vreg_inx) = is_valid ? val : 0; \
+        p->VU.elt<uint32_t>(rd_num + fn * vlmul, vreg_inx) = val; \
         break; \
       case e64: \
-        p->VU.elt<uint64_t>(rd_num + fn * vlmul, vreg_inx) = is_valid ? val : 0; \
+        p->VU.elt<uint64_t>(rd_num + fn * vlmul, vreg_inx) = val; \
         break; \
       } \
        \
-      if (val == 0 && is_valid) { \
+      if (val == 0) { \
         p->VU.vl = i; \
         early_stop = true; \
         break; \
@@ -1639,16 +1575,10 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
 
 #define VI_VFP_LOOP_END \
   } \
-  if (vl != 0 && vl < P.VU.vlmax && P.VU.TZ){ \
-    TAIL_ZERO((P.VU.vsew >> 3) * 1); \
-  }\
   P.VU.vstart = 0; \
 
 #define VI_VFP_LOOP_WIDE_END \
   } \
-  if (vl != 0 && vl < P.VU.vlmax && P.VU.TZ){ \
-    TAIL_ZERO((P.VU.vsew >> 3) * 2); \
-  }\
   P.VU.vstart = 0; \
   set_fp_exceptions;
 
@@ -1658,9 +1588,6 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
   set_fp_exceptions; \
   if (vl > 0) { \
     P.VU.elt<type_sew_t<x>::type>(rd_num, 0) = vd_0.v; \
-    if (P.VU.TZ) { \
-      TAIL_ZERO_REDUCTION(x); \
-    } \
   }
 
 #define VI_VFP_LOOP_CMP_END \
@@ -1676,16 +1603,6 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
       break; \
     }; \
   } \
-  if (vl != 0 && P.VU.TZ){ \
-    for (reg_t i=vl; i<P.VU.vlmax; ++i){ \
-      const int mlen = P.VU.vmlen; \
-      const int midx = (mlen * i) / 64; \
-      const int mpos = (mlen * i) % 64; \
-      uint64_t mmask = (UINT64_MAX << (64 - mlen)) >> (64 - mlen - mpos); \
-      uint64_t &vdi = P.VU.elt<uint64_t>(insn.rd(), midx); \
-      vdi = (vdi & ~mmask);\
-    }\
-  }\
   P.VU.vstart = 0; \
   set_fp_exceptions;
 
diff --git a/riscv/insns/vfmerge_vfm.h b/riscv/insns/vfmerge_vfm.h
index f860f75..ea78165 100644
--- a/riscv/insns/vfmerge_vfm.h
+++ b/riscv/insns/vfmerge_vfm.h
@@ -14,5 +14,4 @@ for (reg_t i=P.VU.vstart; i<vl; ++i) {
   vd = use_first ? rs1 : vs2;
 }
 
-VI_TAIL_ZERO(1);
 P.VU.vstart = 0;
diff --git a/riscv/insns/vfmv_s_f.h b/riscv/insns/vfmv_s_f.h
index fd23dd3..8ff6094 100644
--- a/riscv/insns/vfmv_s_f.h
+++ b/riscv/insns/vfmv_s_f.h
@@ -15,12 +15,5 @@ if (vl > 0) {
   else
     P.VU.elt<uint32_t>(rd_num, 0) = f32(FRS1).v;
 
-  if (P.VU.TZ) {
-    const reg_t max_len = P.VU.VLEN / sew;
-    for (reg_t i = 1; i < max_len; ++i) {
-      P.VU.elt<uint32_t>(rd_num, i) = 0;
-    }
-  }
-
   vl = 0;
 }
diff --git a/riscv/insns/vfmv_v_f.h b/riscv/insns/vfmv_v_f.h
index f2d1271..f323263 100644
--- a/riscv/insns/vfmv_v_f.h
+++ b/riscv/insns/vfmv_v_f.h
@@ -9,5 +9,4 @@ for (reg_t i=P.VU.vstart; i<vl; ++i) {
   vd = rs1;
 }
 
-VI_TAIL_ZERO(1);
 P.VU.vstart = 0;
diff --git a/riscv/insns/vid_v.h b/riscv/insns/vid_v.h
index 4cff192..25422d6 100644
--- a/riscv/insns/vid_v.h
+++ b/riscv/insns/vid_v.h
@@ -29,5 +29,4 @@ for (reg_t i = P.VU.vstart ; i < P.VU.vl; ++i) {
   }
 }
 
-VI_TAIL_ZERO(1);
 P.VU.vstart = 0;
diff --git a/riscv/insns/viota_m.h b/riscv/insns/viota_m.h
index 93e238f..0168373 100644
--- a/riscv/insns/viota_m.h
+++ b/riscv/insns/viota_m.h
@@ -53,4 +53,3 @@ for (reg_t i = 0; i < vl; ++i) {
   }
 }
 
-VI_TAIL_ZERO(1);
diff --git a/riscv/insns/vleff_v.h b/riscv/insns/vleff_v.h
index 148c5bb..e2f39b3 100644
--- a/riscv/insns/vleff_v.h
+++ b/riscv/insns/vleff_v.h
@@ -9,7 +9,6 @@ const reg_t rd_num = insn.rd();
 bool early_stop = false;
 const reg_t vlmul = P.VU.vlmul;
 for (reg_t i = 0; i < P.VU.vlmax && vl != 0; ++i) {
-  bool is_valid = true;
   bool is_zero = false;
   VI_STRIP(i);
   VI_ELEMENT_SKIP(i);
@@ -20,23 +19,23 @@ for (reg_t i = 0; i < P.VU.vlmax && vl != 0; ++i) {
     switch (sew) {
     case e8:
       P.VU.elt<uint8_t>(rd_num + fn * vlmul, vreg_inx) =
-        is_valid ? MMU.load_uint8(baseAddr + (i * nf + fn) * 1, g_vector_mistrap) : 0;
-      is_zero = is_valid && P.VU.elt<uint8_t>(rd_num + fn * vlmul, vreg_inx) == 0;
+        MMU.load_uint8(baseAddr + (i * nf + fn) * 1, g_vector_mistrap);
+      is_zero = P.VU.elt<uint8_t>(rd_num + fn * vlmul, vreg_inx) == 0;
       break;
     case e16:
       P.VU.elt<uint16_t>(rd_num + fn * vlmul, vreg_inx) =
-        is_valid ? MMU.load_uint16(baseAddr + (i * nf + fn) * 2, g_vector_mistrap) : 0;
-      is_zero = is_valid && P.VU.elt<uint16_t>(rd_num + fn * vlmul, vreg_inx) == 0;
+        MMU.load_uint16(baseAddr + (i * nf + fn) * 2, g_vector_mistrap);
+      is_zero = P.VU.elt<uint16_t>(rd_num + fn * vlmul, vreg_inx) == 0;
       break;
     case e32:
       P.VU.elt<uint32_t>(rd_num + fn * vlmul, vreg_inx) =
-        is_valid ? MMU.load_uint32(baseAddr + (i * nf + fn) * 4, g_vector_mistrap) : 0;
-      is_zero = is_valid && P.VU.elt<uint32_t>(rd_num + fn * vlmul, vreg_inx) == 0;
+        MMU.load_uint32(baseAddr + (i * nf + fn) * 4, g_vector_mistrap);
+      is_zero = P.VU.elt<uint32_t>(rd_num + fn * vlmul, vreg_inx) == 0;
       break;
     case e64:
       P.VU.elt<uint64_t>(rd_num + fn * vlmul, vreg_inx) =
-        is_valid ? MMU.load_uint64(baseAddr + (i * nf + fn) * 8, g_vector_mistrap) : 0;
-      is_zero = is_valid && P.VU.elt<uint64_t>(rd_num + fn * vlmul, vreg_inx) == 0;
+        MMU.load_uint64(baseAddr + (i * nf + fn) * 8, g_vector_mistrap);
+      is_zero = P.VU.elt<uint64_t>(rd_num + fn * vlmul, vreg_inx) == 0;
       break;
     }
 
diff --git a/riscv/insns/vmsbf_m.h b/riscv/insns/vmsbf_m.h
index 3047cca..443fcbb 100644
--- a/riscv/insns/vmsbf_m.h
+++ b/riscv/insns/vmsbf_m.h
@@ -30,5 +30,4 @@ for (reg_t i = P.VU.vstart; i < vl; ++i) {
   }
 }
 
-VI_TAIL_ZERO_MASK(rd_num);
 P.VU.vstart = 0;
diff --git a/riscv/insns/vmsif_m.h b/riscv/insns/vmsif_m.h
index 826e7cd..381088b 100644
--- a/riscv/insns/vmsif_m.h
+++ b/riscv/insns/vmsif_m.h
@@ -30,5 +30,4 @@ for (reg_t i = P.VU.vstart ; i < vl; ++i) {
   }
 }
 
-VI_TAIL_ZERO_MASK(rd_num);
 P.VU.vstart = 0;
diff --git a/riscv/insns/vmsof_m.h b/riscv/insns/vmsof_m.h
index 48805f7..d66002d 100644
--- a/riscv/insns/vmsof_m.h
+++ b/riscv/insns/vmsof_m.h
@@ -28,5 +28,4 @@ for (reg_t i = P.VU.vstart ; i < vl; ++i) {
   }
 }
 
-VI_TAIL_ZERO_MASK(rd_num);
 P.VU.vstart = 0;
diff --git a/riscv/insns/vmv_s_x.h b/riscv/insns/vmv_s_x.h
index a3452dc..948b5be 100644
--- a/riscv/insns/vmv_s_x.h
+++ b/riscv/insns/vmv_s_x.h
@@ -24,25 +24,5 @@ if (vl > 0) {
     break;
   }
 
-  if (P.VU.TZ) {
-    const reg_t max_len = P.VU.VLEN / sew;
-    for (reg_t i = 1; i < max_len; ++i) {
-      switch(sew) {
-      case e8:
-        P.VU.elt<uint8_t>(rd_num, i) = 0;
-        break;
-      case e16:
-        P.VU.elt<uint16_t>(rd_num, i) = 0;
-        break;
-      case e32:
-        P.VU.elt<uint32_t>(rd_num, i) = 0;
-        break;
-      default:
-        P.VU.elt<uint64_t>(rd_num, i) = 0;
-        break;
-      }
-    }
-  }
-
   vl = 0;
 }
diff --git a/riscv/insns/vsuxb_v.h b/riscv/insns/vsuxb_v.h
index a6066da..4eea711 100644
--- a/riscv/insns/vsuxb_v.h
+++ b/riscv/insns/vsuxb_v.h
@@ -9,30 +9,25 @@ reg_t vs3 = insn.rd();
 reg_t vlmax = P.VU.vlmax;
 VI_DUPLICATE_VREG(stride, vlmax);
 for (reg_t i = 0; i < vlmax && vl != 0; ++i) {
-  bool is_valid = true;
   VI_ELEMENT_SKIP(i);
   VI_STRIP(i)
 
   switch (P.VU.vsew) {
   case e8:
-    if (is_valid)
-      MMU.store_uint8(baseAddr + index[i],
-                      P.VU.elt<uint8_t>(vs3, vreg_inx), g_vector_mistrap);
+    MMU.store_uint8(baseAddr + index[i],
+                    P.VU.elt<uint8_t>(vs3, vreg_inx), g_vector_mistrap);
     break;
   case e16:
-    if (is_valid)
-      MMU.store_uint8(baseAddr + index[i],
-                      P.VU.elt<uint16_t>(vs3, vreg_inx), g_vector_mistrap);
+    MMU.store_uint8(baseAddr + index[i],
+                    P.VU.elt<uint16_t>(vs3, vreg_inx), g_vector_mistrap);
     break;
   case e32:
-    if (is_valid)
-      MMU.store_uint8(baseAddr + index[i],
-                      P.VU.elt<uint32_t>(vs3, vreg_inx), g_vector_mistrap);
+    MMU.store_uint8(baseAddr + index[i],
+                    P.VU.elt<uint32_t>(vs3, vreg_inx), g_vector_mistrap);
     break;
   case e64:
-    if (is_valid)
-      MMU.store_uint8(baseAddr + index[i],
-                      P.VU.elt<uint64_t>(vs3, vreg_inx), g_vector_mistrap);
+    MMU.store_uint8(baseAddr + index[i],
+                    P.VU.elt<uint64_t>(vs3, vreg_inx), g_vector_mistrap);
     break;
   }
 }
diff --git a/riscv/insns/vsuxe_v.h b/riscv/insns/vsuxe_v.h
index ddc6157..30d7b63 100644
--- a/riscv/insns/vsuxe_v.h
+++ b/riscv/insns/vsuxe_v.h
@@ -10,30 +10,25 @@ reg_t vs3 = insn.rd();
 reg_t vlmax = P.VU.vlmax;
 VI_DUPLICATE_VREG(stride, vlmax);
 for (reg_t i = 0; i < vlmax && vl != 0; ++i) {
-  bool is_valid = true;
   VI_ELEMENT_SKIP(i);
   VI_STRIP(i)
 
   switch (sew) {
   case e8:
-    if (is_valid)
-      MMU.store_uint8(baseAddr + index[i],
-                      P.VU.elt<uint8_t>(vs3, vreg_inx), g_vector_mistrap);
+    MMU.store_uint8(baseAddr + index[i],
+                    P.VU.elt<uint8_t>(vs3, vreg_inx), g_vector_mistrap);
     break;
   case e16:
-    if (is_valid)
-      MMU.store_uint16(baseAddr + index[i],
-                       P.VU.elt<uint16_t>(vs3, vreg_inx), g_vector_mistrap);
+    MMU.store_uint16(baseAddr + index[i],
+                     P.VU.elt<uint16_t>(vs3, vreg_inx), g_vector_mistrap);
     break;
   case e32:
-    if (is_valid)
-      MMU.store_uint32(baseAddr + index[i],
-                       P.VU.elt<uint32_t>(vs3, vreg_inx), g_vector_mistrap);
+    MMU.store_uint32(baseAddr + index[i],
+                     P.VU.elt<uint32_t>(vs3, vreg_inx), g_vector_mistrap);
     break;
   case e64:
-    if (is_valid)
-      MMU.store_uint64(baseAddr + index[i],
-                       P.VU.elt<uint64_t>(vs3, vreg_inx), g_vector_mistrap);
+    MMU.store_uint64(baseAddr + index[i],
+                     P.VU.elt<uint64_t>(vs3, vreg_inx), g_vector_mistrap);
     break;
   }
 }
diff --git a/riscv/insns/vsuxh_v.h b/riscv/insns/vsuxh_v.h
index 0ebdeca..3bd26cf 100644
--- a/riscv/insns/vsuxh_v.h
+++ b/riscv/insns/vsuxh_v.h
@@ -9,25 +9,21 @@ reg_t vs3 = insn.rd();
 reg_t vlmax = P.VU.vlmax;
 VI_DUPLICATE_VREG(stride, vlmax);
 for (reg_t i = 0; i < vlmax && vl != 0; ++i) {
-  bool is_valid = true;
   VI_ELEMENT_SKIP(i);
   VI_STRIP(i)
 
   switch (P.VU.vsew) {
   case e16:
-    if (is_valid)
-      MMU.store_uint16(baseAddr + index[i],
-                       P.VU.elt<uint16_t>(vs3, vreg_inx), g_vector_mistrap);
+    MMU.store_uint16(baseAddr + index[i],
+                     P.VU.elt<uint16_t>(vs3, vreg_inx), g_vector_mistrap);
     break;
   case e32:
-    if (is_valid)
-      MMU.store_uint16(baseAddr + index[i],
-                       P.VU.elt<uint32_t>(vs3, vreg_inx), g_vector_mistrap);
+    MMU.store_uint16(baseAddr + index[i],
+                     P.VU.elt<uint32_t>(vs3, vreg_inx), g_vector_mistrap);
     break;
   case e64:
-    if (is_valid)
-      MMU.store_uint16(baseAddr + index[i],
-                       P.VU.elt<uint64_t>(vs3, vreg_inx), g_vector_mistrap);
+    MMU.store_uint16(baseAddr + index[i],
+                     P.VU.elt<uint64_t>(vs3, vreg_inx), g_vector_mistrap);
     break;
   }
 }
diff --git a/riscv/insns/vsuxw_v.h b/riscv/insns/vsuxw_v.h
index 802643f..b7a7c75 100644
--- a/riscv/insns/vsuxw_v.h
+++ b/riscv/insns/vsuxw_v.h
@@ -9,20 +9,17 @@ reg_t vs3 = insn.rd();
 reg_t vlmax = P.VU.vlmax;
 VI_DUPLICATE_VREG(stride, vlmax);
 for (reg_t i = 0; i < vlmax && vl != 0; ++i) {
-  bool is_valid = true;
   VI_ELEMENT_SKIP(i);
   VI_STRIP(i)
 
   switch (P.VU.vsew) {
   case e32:
-    if (is_valid)
-      MMU.store_uint32(baseAddr + index[i],
-                       P.VU.elt<uint32_t>(vs3, vreg_inx), g_vector_mistrap);
+    MMU.store_uint32(baseAddr + index[i],
+                     P.VU.elt<uint32_t>(vs3, vreg_inx), g_vector_mistrap);
     break;
   case e64:
-    if (is_valid)
-      MMU.store_uint32(baseAddr + index[i],
-                       P.VU.elt<uint64_t>(vs3, vreg_inx), g_vector_mistrap);
+    MMU.store_uint32(baseAddr + index[i],
+                     P.VU.elt<uint64_t>(vs3, vreg_inx), g_vector_mistrap);
     break;
   }
 }
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 2afe6b3..410398d 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -92,7 +92,6 @@ void processor_t::parse_varch_string(const char* s)
   int vlen = 0;
   int elen = 0;
   int slen = 0;
-  bool tz = false;
   std::string token;
   while (!str.empty() && token != str) {
     pos = str.find(delimiter);
@@ -107,8 +106,6 @@ void processor_t::parse_varch_string(const char* s)
       elen = parse_varch(token);
     }else if (token[0] == 's'){
       slen = parse_varch(token);
-    }else if (token[0] == 't'){
-      tz = strtol(&token[1], NULL, 10) == 1;
     }else{
       bad_varch_string(str.c_str());
     }
@@ -122,7 +119,6 @@ void processor_t::parse_varch_string(const char* s)
   VU.VLEN = vlen;
   VU.ELEN = elen;
   VU.SLEN = slen;
-  VU.TZ = tz;
 }
 
 void processor_t::parse_isa_string(const char* str)
diff --git a/riscv/processor.h b/riscv/processor.h
index 8f1a381..b80131c 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -168,7 +168,7 @@ class vectorUnit_t {
     reg_t vstart, vxrm, vxsat, vl, vtype;
     reg_t vediv, vsew, vlmul;
     reg_t ELEN, VLEN, SLEN;
-    bool TZ, vill;
+    bool vill;
 
     std::unordered_map<uint32_t, std::unordered_map<uint64_t, bool>> impl_table;
 
diff --git a/riscv/riscv.ac b/riscv/riscv.ac
index 69c357b..4f98512 100644
--- a/riscv/riscv.ac
+++ b/riscv/riscv.ac
@@ -7,10 +7,10 @@ AC_ARG_WITH(isa,
   AC_DEFINE_UNQUOTED([DEFAULT_ISA], "RV64IMAFDC", [Default value for --isa switch]))
 
 AC_ARG_WITH(varch,
-	[AS_HELP_STRING([--with-varch=v128:e32:s128:t0],
+	[AS_HELP_STRING([--with-varch=v128:e32:s128],
 		[Sets the default vector config])],
   AC_DEFINE_UNQUOTED([DEFAULT_VARCH], "$withval", [Default value for --varch switch]),
-  AC_DEFINE_UNQUOTED([DEFAULT_VARCH], "v128:e32:s128:t0", [Default value for --varch switch]))
+  AC_DEFINE_UNQUOTED([DEFAULT_VARCH], "v128:e32:s128", [Default value for --varch switch]))
 
 
 AC_SEARCH_LIBS([dlopen], [dl dld], [], [