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| author | Andrew Waterman <andrew@sifive.com> | 2019-11-12 11:54:33 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-11-12 11:54:33 -0800 |
| commit | ff81dea8593c6e51b45e7bed230a2cafd56e4caf (patch) | |
| tree | 62bd0cca8bb49199737a5d5532314cb8080d4031 /riscv/processor.h | |
| parent | 3db3d4b1221a145c9703ba5bd82db8b5c6e9ee78 (diff) | |
| parent | c8da0f2446d1261397965e6268d117bb50004ac9 (diff) | |
| download | spike-ff81dea8593c6e51b45e7bed230a2cafd56e4caf.zip spike-ff81dea8593c6e51b45e7bed230a2cafd56e4caf.tar.gz spike-ff81dea8593c6e51b45e7bed230a2cafd56e4caf.tar.bz2 | |
Merge pull request #355 from chihminchao/rvv-0.8-2019-11
rvv-0.8-2019-11
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 68e6249..3e72282 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -200,7 +200,7 @@ class vectorUnit_t { reg_file = 0; } - reg_t set_vl(uint64_t regId, reg_t reqVL, reg_t newType); + reg_t set_vl(int regId, reg_t reqVL, reg_t newType); reg_t get_vlen() { return VLEN; } reg_t get_elen() { return ELEN; } |