From 60e3ed49523c2a1af8b7a115593da42d15515732 Mon Sep 17 00:00:00 2001 From: Chih-Min Chao Date: Mon, 7 Oct 2019 19:46:52 -0700 Subject: rvv: refine vsetvl[i] logic 1. fix the ELAN check for vill 2. handle 'rs1 = x0' 3. make logic more readable Signed-off-by: Chih-Min Chao --- riscv/processor.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'riscv/processor.h') diff --git a/riscv/processor.h b/riscv/processor.h index 68e6249..3e72282 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -200,7 +200,7 @@ class vectorUnit_t { reg_file = 0; } - reg_t set_vl(uint64_t regId, reg_t reqVL, reg_t newType); + reg_t set_vl(int regId, reg_t reqVL, reg_t newType); reg_t get_vlen() { return VLEN; } reg_t get_elen() { return ELEN; } -- cgit v1.1