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path: root/riscv/processor.h
AgeCommit message (Expand)AuthorFilesLines
2019-11-12Add --priv option to control which privilege modes are availableAndrew Waterman1-4/+5
2019-11-11rvv: refine vsetvl[i] logicChih-Min Chao1-1/+1
2019-10-28Implement support for big-endian hostsMarcus Comstedt1-0/+5
2019-09-27Fixed match trigger MATCH_NAPOT case. (#335)fborisovskii1-1/+1
2019-09-18Extends the commit log feature with memory writes. (#324)dave-estes-syzexion1-0/+8
2019-09-18Adds --log-commits commandline option. (#323)dave-estes-syzexion1-0/+3
2019-07-16Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)Tim Newsome1-1/+1
2019-07-12Add debug_mode state bit, rather than overloading dcsr.causeAndrew Waterman1-2/+4
2019-06-14rvv: add varch option parser and initialize vector unitChih-Min Chao1-1/+3
2019-06-14rvv: add vector unit structureChih-Min Chao1-0/+118
2018-09-25Add PMP supportAndrew Waterman1-0/+4
2018-07-10Refactor and fix LR/SC implementation (#217)Andrew Waterman1-3/+0
2018-03-21Implement Hauser misa.C misalignment proposal (#187)Andrew Waterman1-1/+4
2018-03-14Fix a bug caused by moving misa into state_t. (#180)Prashanth Mundkur1-1/+1
2018-03-13Move processor.isa to state.misa, since it really belongs there.Prashanth Mundkur1-2/+2
2018-03-06Narrow the interface used by the processors and memory to the top-level simul...Prashanth Mundkur1-4/+5
2018-03-06Fix install of a missed header from debug_rom.Prashanth Mundkur1-1/+1
2018-03-03Implement clearing-misa.C-while-PC-is-misaligned proposalAndrew Waterman1-0/+5
2017-11-27Rename badaddr to tvalAndrew Waterman1-2/+2
2017-11-27Rename sptbr to satpAndrew Waterman1-1/+1
2017-11-09H-mode no longer existsAndrew Waterman1-1/+0
2017-11-09MPP is now WARLAndrew Waterman1-0/+1
2017-10-20Fix commit-log for Q extension, and for RV32 (#143)Andrew Waterman1-1/+9
2017-09-21Fix corner case in repeated execution (#127)Tim Newsome1-0/+3
2017-08-07Fix multicore debug.Tim Newsome1-6/+0
2017-04-18debug: Checkpoint which somewhat works with OpenOCD v13, but still has some b...Megan Wachs1-0/+1
2017-04-17debug: Move things around, but addresses now conflict with ROM.Megan Wachs1-0/+1
2017-04-17Merge remote-tracking branch 'origin/priv-1.10' into HEADMegan Wachs1-6/+5
2017-03-22riscv: replace rtc device with a real clint implementationWesley W. Terpstra1-1/+1
2017-02-25New counter enable schemeAndrew Waterman1-2/+2
2017-02-10Entering debug mode now jumps to "dynamic rom"Tim Newsome1-0/+6
2017-02-10Implement hartstatus field.Tim Newsome1-0/+1
2017-02-02Fix interrupt delegation for coprocessorsAndrew Waterman1-3/+2
2016-09-09allow MAFDC bits in MISA to be modifiedAndrew Waterman1-0/+1
2016-09-02Merge branch 'master' into triggerTim Newsome1-2/+2
2016-08-31Rename tdata[0-2] to tdata[1-3].Tim Newsome1-12/+14
2016-08-29Rename tdata0--tdata2 to tdata1--tdata3.Tim Newsome1-0/+1
2016-08-26Add (degenerate) performance counter facilityAndrew Waterman1-2/+2
2016-08-25partially update spike to newer debug specAndrew Waterman1-25/+16
2016-08-25Fix spike interactive (-d) modeAndrew Waterman1-3/+2
2016-08-22Implement address and data triggers.Tim Newsome1-1/+151
2016-08-17Allow mstatus.MPP to store bad values; instead, validate on MRETAndrew Waterman1-1/+0
2016-07-28Add support for virtual priv register. (#59)Tim Newsome1-0/+1
2016-06-29Disassemble RVC instructions based on XLENAndrew Waterman1-0/+1
2016-06-22Remove legacy HTIF; implement HTIF directlyAndrew Waterman1-3/+1
2016-06-22Fix paddr_bits computation prior to VM setupAndrew Waterman1-0/+1
2016-05-23Make -H halt the core right out of reset.Tim Newsome1-1/+2
2016-05-23Single step appears to work.Tim Newsome1-0/+8
2016-05-23processor_t unfriends gdbserver_t.Tim Newsome1-3/+3
2016-05-23Add debug_module bus device.Tim Newsome1-2/+0
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