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| author | Bruce Hoult <bruce@hoult.org> | 2019-01-21 21:26:23 -0800 |
|---|---|---|
| committer | Bruce Hoult <bruce@hoult.org> | 2019-01-21 21:26:23 -0800 |
| commit | f04f29d352d413d2bc1ed1c7f60319461746540a (patch) | |
| tree | 6f77099e5ea22f947d0627589135b55ff60cc0ab /riscv/opcodes.h | |
| parent | 412533927340891f3e4d45bed7c3d5ad5d888230 (diff) | |
| download | spike-f04f29d352d413d2bc1ed1c7f60319461746540a.zip spike-f04f29d352d413d2bc1ed1c7f60319461746540a.tar.gz spike-f04f29d352d413d2bc1ed1c7f60319461746540a.tar.bz2 | |
Add FLH and FSH instructions expanding IEEE fp16 in memory to fp32 in registers
Diffstat (limited to 'riscv/opcodes.h')
| -rw-r--r-- | riscv/opcodes.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/riscv/opcodes.h b/riscv/opcodes.h index 34c089e..ff9e096 100644 --- a/riscv/opcodes.h +++ b/riscv/opcodes.h @@ -135,6 +135,16 @@ static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset) MATCH_FSW; } +static uint32_t fsh(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); +static uint32_t fsh(unsigned int src, unsigned int base, uint16_t offset) +{ + return (bits(offset, 11, 5) << 25) | + (bits(src, 4, 0) << 20) | + (base << 15) | + (bits(offset, 4, 0) << 7) | + MATCH_FSH; +} + static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset) { @@ -145,6 +155,15 @@ static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset) MATCH_FSD; } +static uint32_t flh(unsigned int dest, unsigned int base, uint16_t offset) __attribute__ ((unused)); +static uint32_t flh(unsigned int dest, unsigned int base, uint16_t offset) +{ + return (bits(offset, 11, 0) << 20) | + (base << 15) | + (bits(dest, 4, 0) << 7) | + MATCH_FLH; +} + static uint32_t flw(unsigned int dest, unsigned int base, uint16_t offset) __attribute__ ((unused)); static uint32_t flw(unsigned int dest, unsigned int base, uint16_t offset) { |