Add FLH and FSH instructions expanding IEEE fp16 in memory to fp32 in registers

8 files changed, 44 insertions, 0 deletions

diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index 1972542..f662f42 100644
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -577,6 +577,9 @@ bool debug_module_t::perform_abstract_command()
 
         if (write) {
           switch (size) {
+            case 1:
+              write32(debug_abstract, i++, flh(fprnum, ZERO, debug_data_start));
+              break;
             case 2:
               write32(debug_abstract, i++, flw(fprnum, ZERO, debug_data_start));
               break;
@@ -590,6 +593,9 @@ bool debug_module_t::perform_abstract_command()
 
         } else {
           switch (size) {
+            case 1:
+              write32(debug_abstract, i++, fsh(fprnum, ZERO, debug_data_start));
+              break;
             case 2:
               write32(debug_abstract, i++, fsw(fprnum, ZERO, debug_data_start));
               break;
diff --git a/riscv/decode.h b/riscv/decode.h
index f9e3b6f..71871cc 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -231,6 +231,7 @@ private:
 #define isBoxedF64(r) ((r.v[1] + 1) == 0)
 #define unboxF64(r) (isBoxedF64(r) ? r.v[0] : defaultNaNF64UI)
 typedef float128_t freg_t;
+inline float16_t f16(uint16_t v) { return { v }; }
 inline float32_t f32(uint32_t v) { return { v }; }
 inline float64_t f64(uint64_t v) { return { v }; }
 inline float32_t f32(freg_t r) { return f32(unboxF32(r)); }
diff --git a/riscv/encoding.h b/riscv/encoding.h
index dadbbd0..544e3dc 100644
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -580,12 +580,16 @@
 #define MASK_FCVT_Q_LU  0xfff0007f
 #define MATCH_FMV_Q_X 0xf6000053
 #define MASK_FMV_Q_X  0xfff0707f
+#define MATCH_FLH 0x1007
+#define MASK_FLH  0x707f
 #define MATCH_FLW 0x2007
 #define MASK_FLW  0x707f
 #define MATCH_FLD 0x3007
 #define MASK_FLD  0x707f
 #define MATCH_FLQ 0x4007
 #define MASK_FLQ  0x707f
+#define MATCH_FSH 0x1027
+#define MASK_FSH  0x707f
 #define MATCH_FSW 0x2027
 #define MASK_FSW  0x707f
 #define MATCH_FSD 0x3027
@@ -1154,9 +1158,11 @@ DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
 DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
 DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
 DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
+DECLARE_INSN(flh, MATCH_FLH, MASK_FLH)
 DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
 DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
 DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
+DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH)
 DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
 DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
 DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ)
diff --git a/riscv/insns/flh.h b/riscv/insns/flh.h
new file mode 100644
index 0000000..3c96dbc
--- /dev/null
+++ b/riscv/insns/flh.h
@@ -0,0 +1,4 @@
+require_extension('F');
+//require_extension('V');
+require_fp;
+WRITE_FRD(f16_to_f32(f16(MMU.load_uint16(RS1 + insn.i_imm()))));
diff --git a/riscv/insns/fsh.h b/riscv/insns/fsh.h
new file mode 100644
index 0000000..61c3ef9
--- /dev/null
+++ b/riscv/insns/fsh.h
@@ -0,0 +1,4 @@
+require_extension('F');
+//require_extension('V');
+require_fp;
+MMU.store_uint16(RS1 + insn.s_imm(), f32_to_f16(f32(unboxF32(FRS2))).v);
diff --git a/riscv/opcodes.h b/riscv/opcodes.h
index 34c089e..ff9e096 100644
--- a/riscv/opcodes.h
+++ b/riscv/opcodes.h
@@ -135,6 +135,16 @@ static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset)
     MATCH_FSW;
 }
 
+static uint32_t fsh(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused));
+static uint32_t fsh(unsigned int src, unsigned int base, uint16_t offset)
+{
+  return (bits(offset, 11, 5) << 25) |
+    (bits(src, 4, 0) << 20) |
+    (base << 15) |
+    (bits(offset, 4, 0) << 7) |
+    MATCH_FSH;
+}
+
 static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused));
 static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset)
 {
@@ -145,6 +155,15 @@ static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset)
     MATCH_FSD;
 }
 
+static uint32_t flh(unsigned int dest, unsigned int base, uint16_t offset) __attribute__ ((unused));
+static uint32_t flh(unsigned int dest, unsigned int base, uint16_t offset)
+{
+  return (bits(offset, 11, 0) << 20) |
+    (base << 15) |
+    (bits(dest, 4, 0) << 7) |
+    MATCH_FLH;
+}
+
 static uint32_t flw(unsigned int dest, unsigned int base, uint16_t offset) __attribute__ ((unused));
 static uint32_t flw(unsigned int dest, unsigned int base, uint16_t offset)
 {
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 80755e7..0a85de3 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -189,6 +189,7 @@ riscv_insn_list = \
 	fle_d \
 	fle_q \
 	fle_s \
+	flh \
 	flq \
 	flt_d \
 	flt_q \
@@ -229,6 +230,7 @@ riscv_insn_list = \
 	fsgnjx_d \
 	fsgnjx_q \
 	fsgnjx_s \
+	fsh \
 	fsq \
 	fsqrt_d \
 	fsqrt_q \
diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc
index 81264dd..e622216 100644
--- a/spike_main/disasm.cc
+++ b/spike_main/disasm.cc
@@ -356,10 +356,12 @@ disassembler_t::disassembler_t(int xlen)
   DEFINE_XAMO_LR(lr_d)
   DEFINE_XAMO(sc_d)
 
+  DEFINE_FLOAD(flh)
   DEFINE_FLOAD(flw)
   DEFINE_FLOAD(fld)
   DEFINE_FLOAD(flq)
 
+  DEFINE_FSTORE(fsh)
   DEFINE_FSTORE(fsw)
   DEFINE_FSTORE(fsd)
   DEFINE_FSTORE(fsq)