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| author | Ryan Buchner <ryan.buchner@arilinc.com> | 2023-04-17 18:53:27 -0700 |
|---|---|---|
| committer | rbuchner <ryan.buchner@arilinc.com> | 2023-05-11 23:00:58 -0700 |
| commit | 3286d262eb42f414e7e43c734532f309dee9fe81 (patch) | |
| tree | 6d5dc02a01d222e803a733de32a622c855ccdfcb /riscv/mmu.h | |
| parent | dc3eb2d9e3b805ed1a1416c1e66584cf6520d0f1 (diff) | |
| download | spike-3286d262eb42f414e7e43c734532f309dee9fe81.zip spike-3286d262eb42f414e7e43c734532f309dee9fe81.tar.gz spike-3286d262eb42f414e7e43c734532f309dee9fe81.tar.bz2 | |
Rename RISCV_XLATE_VIRT to RISCV_XLATE_FORCED_VIRT
More readable/understandable.
Diffstat (limited to 'riscv/mmu.h')
| -rw-r--r-- | riscv/mmu.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index ef054cf..d63a43f 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -51,7 +51,7 @@ public: mmu_t(simif_t* sim, endianness_t endianness, processor_t* proc); ~mmu_t(); -#define RISCV_XLATE_VIRT (1U << 0) +#define RISCV_XLATE_FORCED_VIRT (1U << 0) #define RISCV_XLATE_VIRT_HLVX (1U << 1) #define RISCV_XLATE_LR (1U << 2) @@ -81,12 +81,12 @@ public: template<typename T> T guest_load(reg_t addr) { - return load<T>(addr, RISCV_XLATE_VIRT); + return load<T>(addr, RISCV_XLATE_FORCED_VIRT); } template<typename T> T guest_load_x(reg_t addr) { - return load<T>(addr, RISCV_XLATE_VIRT|RISCV_XLATE_VIRT_HLVX); + return load<T>(addr, RISCV_XLATE_FORCED_VIRT|RISCV_XLATE_VIRT_HLVX); } template<typename T> @@ -108,7 +108,7 @@ public: template<typename T> void guest_store(reg_t addr, T val) { - store(addr, val, RISCV_XLATE_VIRT); + store(addr, val, RISCV_XLATE_FORCED_VIRT); } // AMO/Zicbom faults should be reported as store faults |