[xcc,sim,opcodes] added more RVC instructions

20 files changed, 65 insertions, 1 deletions

diff --git a/riscv/insns/c_add.h b/riscv/insns/c_add.h
new file mode 100644
index 0000000..2170d69
--- /dev/null
+++ b/riscv/insns/c_add.h
@@ -0,0 +1,2 @@
+require_rvc;
+CRD = CRS1 + CRS2;
diff --git a/riscv/insns/c_add3.h b/riscv/insns/c_add3.h
new file mode 100644
index 0000000..914c85d
--- /dev/null
+++ b/riscv/insns/c_add3.h
@@ -0,0 +1,2 @@
+require_rvc;
+CRDS = CRS1S + CRS2BS;
diff --git a/riscv/insns/c_addi.h b/riscv/insns/c_addi.h
index 4a5a0af..c716f69 100644
--- a/riscv/insns/c_addi.h
+++ b/riscv/insns/c_addi.h
@@ -1,2 +1,10 @@
 require_rvc;
-CRD = sext_xprlen(CRS2 + CIMM6);
+if(CRD_REGNUM == 0)
+{
+  reg_t temp = npc;
+  npc = CRS1;
+  if(CIMM6 & 0x20)
+    RA = temp;
+}
+else
+  CRD = sext_xprlen(CRS2 + CIMM6);
diff --git a/riscv/insns/c_and3.h b/riscv/insns/c_and3.h
new file mode 100644
index 0000000..b506d6a
--- /dev/null
+++ b/riscv/insns/c_and3.h
@@ -0,0 +1,2 @@
+require_rvc;
+CRDS = CRS1S & CRS2BS;
diff --git a/riscv/insns/c_fld.h b/riscv/insns/c_fld.h
new file mode 100644
index 0000000..a726039
--- /dev/null
+++ b/riscv/insns/c_fld.h
@@ -0,0 +1,3 @@
+require_rvc;
+require_fp;
+FCRDS = mmu.load_int64(CRS1S+CIMM5*8);
diff --git a/riscv/insns/c_flw.h b/riscv/insns/c_flw.h
new file mode 100644
index 0000000..cdb7221
--- /dev/null
+++ b/riscv/insns/c_flw.h
@@ -0,0 +1,3 @@
+require_rvc;
+require_fp;
+FCRDS = mmu.load_int32(CRS1S+CIMM5*4);
diff --git a/riscv/insns/c_fsd.h b/riscv/insns/c_fsd.h
new file mode 100644
index 0000000..20814fd
--- /dev/null
+++ b/riscv/insns/c_fsd.h
@@ -0,0 +1,3 @@
+require_rvc;
+require_fp;
+mmu.store_uint64(CRS1S+CIMM5*8, FCRS2S);
diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h
new file mode 100644
index 0000000..1d21629
--- /dev/null
+++ b/riscv/insns/c_fsw.h
@@ -0,0 +1,3 @@
+require_rvc;
+require_fp;
+mmu.store_uint32(CRS1S+CIMM5*4, FCRS2S);
diff --git a/riscv/insns/c_ld0.h b/riscv/insns/c_ld0.h
new file mode 100644
index 0000000..f51a966
--- /dev/null
+++ b/riscv/insns/c_ld0.h
@@ -0,0 +1,3 @@
+require_rvc;
+require_xpr64;
+CRD = mmu.load_int64(CRS1);
diff --git a/riscv/insns/c_lw0.h b/riscv/insns/c_lw0.h
new file mode 100644
index 0000000..d263a80
--- /dev/null
+++ b/riscv/insns/c_lw0.h
@@ -0,0 +1,2 @@
+require_rvc;
+CRD = mmu.load_int32(CRS1);
diff --git a/riscv/insns/c_or3.h b/riscv/insns/c_or3.h
new file mode 100644
index 0000000..143e2ae
--- /dev/null
+++ b/riscv/insns/c_or3.h
@@ -0,0 +1,2 @@
+require_rvc;
+CRDS = CRS1S | CRS2BS;
diff --git a/riscv/insns/c_slli.h b/riscv/insns/c_slli.h
new file mode 100644
index 0000000..5026767
--- /dev/null
+++ b/riscv/insns/c_slli.h
@@ -0,0 +1,5 @@
+require_rvc;
+if(xpr64)
+  CRDS = CRDS << CIMM5U;
+else
+  CRDS = sext32(CRDS << CIMM5U);
diff --git a/riscv/insns/c_slli32.h b/riscv/insns/c_slli32.h
new file mode 100644
index 0000000..1e3e958
--- /dev/null
+++ b/riscv/insns/c_slli32.h
@@ -0,0 +1,3 @@
+require_rvc;
+require_xpr64;
+CRDS = CRDS << (32+CIMM5U);
diff --git a/riscv/insns/c_slliw.h b/riscv/insns/c_slliw.h
new file mode 100644
index 0000000..9e428f5
--- /dev/null
+++ b/riscv/insns/c_slliw.h
@@ -0,0 +1,3 @@
+require_rvc;
+require_xpr64;
+CRDS = sext32(CRDS << CIMM5U);
diff --git a/riscv/insns/c_srai.h b/riscv/insns/c_srai.h
new file mode 100644
index 0000000..aa33424
--- /dev/null
+++ b/riscv/insns/c_srai.h
@@ -0,0 +1,5 @@
+require_rvc;
+if(xpr64)
+  CRDS = sreg_t(CRDS) >> CIMM5U;
+else
+  CRDS = sext32(int32_t(CRDS) >> CIMM5U);
diff --git a/riscv/insns/c_srai32.h b/riscv/insns/c_srai32.h
new file mode 100644
index 0000000..ca7b024
--- /dev/null
+++ b/riscv/insns/c_srai32.h
@@ -0,0 +1,3 @@
+require_rvc;
+require_xpr64;
+CRDS = sreg_t(CRDS) >> (32+CIMM5U);
diff --git a/riscv/insns/c_srli.h b/riscv/insns/c_srli.h
new file mode 100644
index 0000000..56e0681
--- /dev/null
+++ b/riscv/insns/c_srli.h
@@ -0,0 +1,5 @@
+require_rvc;
+if(xpr64)
+  CRDS = CRDS >> CIMM5U;
+else
+  CRDS = sext32(uint32_t(CRDS) >> CIMM5U);
diff --git a/riscv/insns/c_srli32.h b/riscv/insns/c_srli32.h
new file mode 100644
index 0000000..4f5b8ea
--- /dev/null
+++ b/riscv/insns/c_srli32.h
@@ -0,0 +1,3 @@
+require_rvc;
+require_xpr64;
+CRDS = CRDS >> (32+CIMM5U);
diff --git a/riscv/insns/c_sub.h b/riscv/insns/c_sub.h
new file mode 100644
index 0000000..9fd8932
--- /dev/null
+++ b/riscv/insns/c_sub.h
@@ -0,0 +1,2 @@
+require_rvc;
+CRD = CRS1 - CRS2;
diff --git a/riscv/insns/c_sub3.h b/riscv/insns/c_sub3.h
new file mode 100644
index 0000000..53afc84
--- /dev/null
+++ b/riscv/insns/c_sub3.h
@@ -0,0 +1,2 @@
+require_rvc;
+CRDS = CRS1S - CRS2BS;