rvv: aad fp16 support for vfwxxx.[wv]v

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

10 files changed, 47 insertions, 8 deletions

diff --git a/riscv/decode.h b/riscv/decode.h
index cce9f04..d209af3 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -1956,20 +1956,26 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
   VI_VFP_LOOP_END
 
 
-#define VI_VFP_VV_LOOP_WIDE(BODY) \
+#define VI_VFP_VV_LOOP_WIDE(BODY16, BODY32) \
   VI_CHECK_DSS(true); \
   VI_VFP_LOOP_BASE \
   switch(P.VU.vsew) { \
+    case e16: {\
+      float32_t &vd = P.VU.elt<float32_t>(rd_num, i, true); \
+      float32_t vs2 = f16_to_f32(P.VU.elt<float16_t>(rs2_num, i)); \
+      float32_t vs1 = f16_to_f32(P.VU.elt<float16_t>(rs1_num, i)); \
+      BODY16; \
+      set_fp_exceptions; \
+      break; \
+    }\
     case e32: {\
       float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \
       float64_t vs2 = f32_to_f64(P.VU.elt<float32_t>(rs2_num, i)); \
       float64_t vs1 = f32_to_f64(P.VU.elt<float32_t>(rs1_num, i)); \
-      BODY; \
+      BODY32; \
       set_fp_exceptions; \
       break; \
     }\
-    case e16: \
-    case e8: \
     default: \
       require(0); \
       break; \
@@ -2003,20 +2009,26 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
   DEBUG_RVV_FP_VV; \
   VI_VFP_LOOP_END
 
-#define VI_VFP_WV_LOOP_WIDE(BODY) \
+#define VI_VFP_WV_LOOP_WIDE(BODY16, BODY32) \
   VI_CHECK_DDS(true); \
   VI_VFP_LOOP_BASE \
   switch(P.VU.vsew) { \
+    case e16: {\
+      float32_t &vd = P.VU.elt<float32_t>(rd_num, i, true); \
+      float32_t vs2 = P.VU.elt<float32_t>(rs2_num, i); \
+      float32_t vs1 = f16_to_f32(P.VU.elt<float16_t>(rs1_num, i)); \
+      BODY16; \
+      set_fp_exceptions; \
+      break; \
+    }\
     case e32: {\
       float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \
       float64_t vs2 = P.VU.elt<float64_t>(rs2_num, i); \
       float64_t vs1 = f32_to_f64(P.VU.elt<float32_t>(rs1_num, i)); \
-      BODY; \
+      BODY32; \
       set_fp_exceptions; \
       break; \
     }\
-    case e16: \
-    case e8: \
     default: \
       require(0); \
   }; \
diff --git a/riscv/insns/vfwadd_vv.h b/riscv/insns/vfwadd_vv.h
index 0665cdc..7255a50 100644
--- a/riscv/insns/vfwadd_vv.h
+++ b/riscv/insns/vfwadd_vv.h
@@ -1,5 +1,8 @@
 // vfwadd.vv vd, vs2, vs1
 VI_VFP_VV_LOOP_WIDE
 ({
+  vd = f32_add(vs2, vs1);
+},
+{
   vd = f64_add(vs2, vs1);
 })
diff --git a/riscv/insns/vfwadd_wv.h b/riscv/insns/vfwadd_wv.h
index 675ef22..c1ed038 100644
--- a/riscv/insns/vfwadd_wv.h
+++ b/riscv/insns/vfwadd_wv.h
@@ -1,5 +1,8 @@
 // vfwadd.wv vd, vs2, vs1
 VI_VFP_WV_LOOP_WIDE
 ({
+  vd = f32_add(vs2, vs1);
+},
+{
   vd = f64_add(vs2, vs1);
 })
diff --git a/riscv/insns/vfwmacc_vv.h b/riscv/insns/vfwmacc_vv.h
index 99839af..a654198 100644
--- a/riscv/insns/vfwmacc_vv.h
+++ b/riscv/insns/vfwmacc_vv.h
@@ -1,5 +1,8 @@
 // vfwmacc.vv vd, vs2, vs1
 VI_VFP_VV_LOOP_WIDE
 ({
+  vd = f32_mulAdd(vs1, vs2, vd);
+},
+{
   vd = f64_mulAdd(vs1, vs2, vd);
 })
diff --git a/riscv/insns/vfwmsac_vv.h b/riscv/insns/vfwmsac_vv.h
index 8157170..9dc4073 100644
--- a/riscv/insns/vfwmsac_vv.h
+++ b/riscv/insns/vfwmsac_vv.h
@@ -1,5 +1,8 @@
 // vfwmsac.vv  vd, vs2, vs1
 VI_VFP_VV_LOOP_WIDE
 ({
+  vd = f32_mulAdd(vs1, vs2, f32(vd.v ^ F32_SIGN));
+},
+{
   vd = f64_mulAdd(vs1, vs2, f64(vd.v ^ F64_SIGN));
 })
diff --git a/riscv/insns/vfwmul_vv.h b/riscv/insns/vfwmul_vv.h
index f8e717e..2ce38e6 100644
--- a/riscv/insns/vfwmul_vv.h
+++ b/riscv/insns/vfwmul_vv.h
@@ -1,5 +1,8 @@
 // vfwmul.vv vd, vs2, vs1
 VI_VFP_VV_LOOP_WIDE
 ({
+  vd = f32_mul(vs2, vs1);
+},
+{
   vd = f64_mul(vs2, vs1);
 })
diff --git a/riscv/insns/vfwnmacc_vv.h b/riscv/insns/vfwnmacc_vv.h
index 3dcba1d..bf863e0 100644
--- a/riscv/insns/vfwnmacc_vv.h
+++ b/riscv/insns/vfwnmacc_vv.h
@@ -1,5 +1,8 @@
 // vfwnmacc.vv vd, vs2, vs1
 VI_VFP_VV_LOOP_WIDE
 ({
+  vd = f32_mulAdd(f32(vs1.v ^ F32_SIGN), vs2, f32(vd.v ^ F32_SIGN));
+},
+{
   vd = f64_mulAdd(f64(vs1.v ^ F64_SIGN), vs2, f64(vd.v ^ F64_SIGN));
 })
diff --git a/riscv/insns/vfwnmsac_vv.h b/riscv/insns/vfwnmsac_vv.h
index d2447e1..ce97749 100644
--- a/riscv/insns/vfwnmsac_vv.h
+++ b/riscv/insns/vfwnmsac_vv.h
@@ -1,5 +1,8 @@
 // vfwnmsac.vv vd, vs2, vs1
 VI_VFP_VV_LOOP_WIDE
 ({
+  vd = f32_mulAdd(f32(vs1.v ^ F32_SIGN), vs2, vd);
+},
+{
   vd = f64_mulAdd(f64(vs1.v ^ F64_SIGN), vs2, vd);
 })
diff --git a/riscv/insns/vfwsub_vv.h b/riscv/insns/vfwsub_vv.h
index 0a72fea..ce08e36 100644
--- a/riscv/insns/vfwsub_vv.h
+++ b/riscv/insns/vfwsub_vv.h
@@ -1,5 +1,8 @@
 // vfwsub.vv vd, vs2, vs1
 VI_VFP_VV_LOOP_WIDE
 ({
+  vd = f32_sub(vs2, vs1);
+},
+{
   vd = f64_sub(vs2, vs1);
 })
diff --git a/riscv/insns/vfwsub_wv.h b/riscv/insns/vfwsub_wv.h
index 4c6fcf6..eef904d 100644
--- a/riscv/insns/vfwsub_wv.h
+++ b/riscv/insns/vfwsub_wv.h
@@ -1,5 +1,8 @@
 // vfwsub.wv vd, vs2, vs1
 VI_VFP_WV_LOOP_WIDE
 ({
+  vd = f32_sub(vs2, vs1);
+},
+{
   vd = f64_sub(vs2, vs1);
 })