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author | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
commit | 68aeeb5500521ff52c216862f9a653b64191f3ad (patch) | |
tree | 407230ff48f79f177a792451598d9b2b6e3d34a0 /riscv/insns/aes64ks1i.h | |
parent | 191634d2854dfed448fc323195f9b65c305e2d77 (diff) | |
parent | 03be4ae6c7b8e9865083b61427ff9724c7706fcf (diff) | |
download | spike-plic_uart_v1.zip spike-plic_uart_v1.tar.gz spike-plic_uart_v1.tar.bz2 |
Merge branch 'master' into plic_uart_v1plic_uart_v1
Diffstat (limited to 'riscv/insns/aes64ks1i.h')
-rw-r--r-- | riscv/insns/aes64ks1i.h | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/riscv/insns/aes64ks1i.h b/riscv/insns/aes64ks1i.h index fff7109..c7354d6 100644 --- a/riscv/insns/aes64ks1i.h +++ b/riscv/insns/aes64ks1i.h @@ -10,16 +10,13 @@ uint8_t round_consts [10] = { uint8_t enc_rcon = insn.rcon() ; -if(enc_rcon > 0xA) { - // Invalid opcode. - throw trap_illegal_instruction(0); -} +require(enc_rcon <= 0xA); uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF ; uint8_t rcon = 0 ; uint64_t result ; -if(enc_rcon != 0xA) { +if (enc_rcon != 0xA) { temp = (temp >> 8) | (temp << 24); // Rotate right by 8 rcon = round_consts[enc_rcon]; } |