From ce34edb0eecec520d6d2cfec5bda57ca90a69f14 Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Wed, 10 Aug 2022 22:55:07 +0800 Subject: Add space between if/while/switch and '(' Add space between ')' and '{' --- riscv/insns/aes64ks1i.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'riscv/insns/aes64ks1i.h') diff --git a/riscv/insns/aes64ks1i.h b/riscv/insns/aes64ks1i.h index fff7109..3ce3c3f 100644 --- a/riscv/insns/aes64ks1i.h +++ b/riscv/insns/aes64ks1i.h @@ -10,7 +10,7 @@ uint8_t round_consts [10] = { uint8_t enc_rcon = insn.rcon() ; -if(enc_rcon > 0xA) { +if (enc_rcon > 0xA) { // Invalid opcode. throw trap_illegal_instruction(0); } @@ -19,7 +19,7 @@ uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF ; uint8_t rcon = 0 ; uint64_t result ; -if(enc_rcon != 0xA) { +if (enc_rcon != 0xA) { temp = (temp >> 8) | (temp << 24); // Rotate right by 8 rcon = round_consts[enc_rcon]; } -- cgit v1.1 From 86d9fe49eda1fff863a43e682015216a25cc72f3 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 11 Oct 2022 15:19:00 -0700 Subject: Set tval on illegal subforms of aes64ks1i h/t @YenHaoChen --- riscv/insns/aes64ks1i.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'riscv/insns/aes64ks1i.h') diff --git a/riscv/insns/aes64ks1i.h b/riscv/insns/aes64ks1i.h index 3ce3c3f..c7354d6 100644 --- a/riscv/insns/aes64ks1i.h +++ b/riscv/insns/aes64ks1i.h @@ -10,10 +10,7 @@ uint8_t round_consts [10] = { uint8_t enc_rcon = insn.rcon() ; -if (enc_rcon > 0xA) { - // Invalid opcode. - throw trap_illegal_instruction(0); -} +require(enc_rcon <= 0xA); uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF ; uint8_t rcon = 0 ; -- cgit v1.1