Merge branch 'master' into plic_uart_v1plic_uart_v1

1 files changed, 20 insertions, 28 deletions

diff --git a/riscv/execute.cc b/riscv/execute.cc
index 98e3cdb..f0bb946 100644
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -133,7 +133,7 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn)
       if (prefix == 'c')
         fprintf(log_file, " c%d_%s ", rd, csr_name(rd));
       else
-        fprintf(log_file, " %c%2d ", prefix, rd);
+        fprintf(log_file, " %c%-2d ", prefix, rd);
       if (is_vreg)
         commit_log_print_value(log_file, size, &p->VU.elt<uint8_t>(rd, 0));
       else
@@ -154,13 +154,9 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn)
   }
   fprintf(log_file, "\n");
 }
-#else
-static void commit_log_reset(processor_t* p) {}
-static void commit_log_stash_privilege(processor_t* p) {}
-static void commit_log_print_insn(processor_t* p, reg_t pc, insn_t insn) {}
 #endif
 
-inline void processor_t::update_histogram(reg_t pc)
+inline void processor_t::update_histogram(reg_t UNUSED pc)
 {
 #ifdef RISCV_ENABLE_HISTOGRAM
   pc_histogram[pc]++;
@@ -172,8 +168,10 @@ inline void processor_t::update_histogram(reg_t pc)
 // function calls.
 static inline reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
 {
+#ifdef RISCV_ENABLE_COMMITLOG
   commit_log_reset(p);
   commit_log_stash_privilege(p);
+#endif
   reg_t npc;
 
   try {
@@ -238,19 +236,18 @@ void processor_t::step(size_t n)
     mmu_t* _mmu = mmu;
 
     #define advance_pc() \
-     if (unlikely(invalid_pc(pc))) { \
-       switch (pc) { \
-         case PC_SERIALIZE_BEFORE: state.serialized = true; break; \
-         case PC_SERIALIZE_AFTER: ++instret; break; \
-         case PC_SERIALIZE_WFI: n = ++instret; break; \
-         default: abort(); \
-       } \
-       pc = state.pc; \
-       break; \
-     } else { \
-       state.pc = pc; \
-       instret++; \
-     }
+      if (unlikely(invalid_pc(pc))) { \
+        switch (pc) { \
+          case PC_SERIALIZE_BEFORE: state.serialized = true; break; \
+          case PC_SERIALIZE_AFTER: ++instret; break; \
+          default: abort(); \
+        } \
+        pc = state.pc; \
+        break; \
+      } else { \
+        state.pc = pc; \
+        instret++; \
+      }
 
     try
     {
@@ -312,15 +309,6 @@ void processor_t::step(size_t n)
     catch (triggers::matched_t& t)
     {
       if (mmu->matched_trigger) {
-        // This exception came from the MMU. That means the instruction hasn't
-        // fully executed yet. We start it again, but this time it won't throw
-        // an exception because matched_trigger is already set. (All memory
-        // instructions are idempotent so restarting is safe.)
-
-        insn_fetch_t fetch = mmu->load_insn(pc);
-        pc = execute_insn(this, pc, fetch);
-        advance_pc();
-
         delete mmu->matched_trigger;
         mmu->matched_trigger = NULL;
       }
@@ -337,6 +325,10 @@ void processor_t::step(size_t n)
           abort();
       }
     }
+    catch(trap_debug_mode&)
+    {
+      enter_debug_mode(DCSR_CAUSE_SWBP);
+    }
     catch (wait_for_interrupt_t &t)
     {
       // Return to the outer simulation loop, which gives other devices/harts a