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AgeCommit message (Expand)AuthorFilesLines
2022-10-06Don't use reexecution as the means to implement trigger-afterAndrew Waterman1-9/+0
2022-10-04Suppress most unused variable warningsAndrew Waterman1-1/+1
2022-10-04Delete functions that are actually unusedAndrew Waterman1-4/+0
2022-08-10Fix code indentation in processor.cc, interactive.cc, debug_module.h/ccWeiwei Li1-12/+12
2022-08-10Add #ifdef RISCV_ENABLE_COMMITLOG for commitlog related codeWeiwei Li1-0/+2
2022-06-01Remove the now-unused PC_SERIALIZE_WFIKip Walker1-1/+0
2022-05-19Move ebreak* logic from take_trap into instructions. (#1006)Tim Newsome1-0/+4
2022-05-04Fix the padding of register names in the log (#987)Shaked Flur1-1/+1
2022-04-05Move trigger match logic into triggers.ccTim Newsome1-1/+1
2022-04-05trigger_matched_t -> triggers::matched_tTim Newsome1-1/+1
2022-03-30Replace state.mcontrol with TM.triggers.Tim Newsome1-1/+1
2022-03-30mcontrol_action_t -> triggers::action_tTim Newsome1-2/+2
2022-02-19Make comment more germaneAndrew Waterman1-5/+1
2022-02-18Split out MINSTRET and MCYCLERupert Swarbrick1-0/+8
2021-11-04Report proper GVA bit on breakpoint trapsScott Johnson1-1/+1
2021-11-04Add gva field to trap_breakpointScott Johnson1-1/+1
2021-11-03Use appropriate subclass for breakpoint trapScott Johnson1-1/+1
2021-09-29Convert vl to csr_tScott Johnson1-1/+1
2021-09-26Convert dcsr to csr_tScott Johnson1-1/+1
2021-09-16Convert minstret to csr_tScott Johnson1-1/+1
2021-07-28Inline execute_insnAndrew Waterman1-1/+1
2021-07-17commitlog: add toggle for wfiChih-Min Chao1-1/+3
2021-06-02Remove Duff's Device in main simulation loop (#721)Andrew Waterman1-43/+12
2021-02-09Fix commit log for WFI instructionsAndrew Waterman1-0/+3
2021-01-27Increment minstret when WFI completes (#636)Scott Johnson1-1/+1
2020-10-26commitlog: fix compilation warningChih-Min Chao1-1/+1
2020-10-06rvv: commitlog: get hartid directlyChih-Min Chao1-2/+1
2020-09-29Adding symbol lookup when --enable-commitlog is enabled (#558)sthiruva1-0/+5
2020-09-28Add core id to lines generated by --log-commits (#556)sthiruva1-0/+4
2020-07-08Extend trap classes to pass more informationAnup Patel1-1/+1
2020-07-02commitlog: support csr accessChih-Min Chao1-1/+5
2020-07-02commitlog: simplify print_value pathChih-Min Chao1-26/+27
2020-07-02commitlog: extend hint bit to record csr accessChih-Min Chao1-2/+6
2020-06-17rvv: commitlog: fix fractional lmul dumpChih-Min Chao1-2/+2
2020-06-04rvv: fix compilation warningChih-Min Chao1-1/+1
2020-05-28rvv: extenc VU structure to support 0.9 new fieldsChih-Min Chao1-1/+5
2020-05-26Report haltgroup halt cause, per the debug spec. (#473)Tim Newsome1-1/+3
2020-04-29rvv: commitlog: report status when memory trap occurs in vector load/storeChih-Min Chao1-6/+25
2020-03-27Write execution logs to a named log file (#409)Rupert Swarbrick1-27/+37
2020-03-23commitlog: fix wrong dump when exception occursChih-Min Chao1-7/+14
2020-03-09commitlog: enhance vector dumpChih-Min Chao1-5/+14
2020-02-20commitlog: print vsew in bitChih-Min Chao1-1/+1
2020-02-18commitlog: fix printf format warningChih-Min Chao1-1/+1
2020-01-22commitlog: extend reg record to keep multiple accesssChih-Min Chao1-15/+55
2020-01-13commitlog: extend load/store record to keep multiple accessChih-Min Chao1-7/+9
2019-12-16extend the commit and memory writes log feature with memory reads (#370)John Ingalls1-5/+11
2019-09-18Extends the commit log feature with memory writes. (#324)dave-estes-syzexion1-5/+14
2019-09-18Adds --log-commits commandline option. (#323)dave-estes-syzexion1-1/+3
2019-07-12Add debug_mode state bit, rather than overloading dcsr.causeAndrew Waterman1-3/+3
2019-06-18rvv: extend interactive debugChih-Min Chao1-1/+0
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