From a8245e92fb80023cead1a9c6efb00ff98deb5a09 Mon Sep 17 00:00:00 2001 From: Shaked Flur Date: Wed, 4 May 2022 19:43:38 +0100 Subject: Fix the padding of register names in the log (#987) This fix print x5 as "x5 ", instead of "x 5". --- riscv/execute.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'riscv/execute.cc') diff --git a/riscv/execute.cc b/riscv/execute.cc index 98e3cdb..a6ea7a4 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -133,7 +133,7 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn) if (prefix == 'c') fprintf(log_file, " c%d_%s ", rd, csr_name(rd)); else - fprintf(log_file, " %c%2d ", prefix, rd); + fprintf(log_file, " %c%-2d ", prefix, rd); if (is_vreg) commit_log_print_value(log_file, size, &p->VU.elt(rd, 0)); else -- cgit v1.1 From a0298a33e7b2091ba8d9f3a20838d96dc1164cac Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 19 May 2022 17:11:07 -0700 Subject: Move ebreak* logic from take_trap into instructions. (#1006) Now that logic only affects ebreak instructions, and does not affect triggers that also cause a trap to be taken. Fixes #725. Although like Paul, I don't have a test for this case. Introduce trap_debug_mode so so ebreak instructions can force entry into debug mode. --- riscv/execute.cc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'riscv/execute.cc') diff --git a/riscv/execute.cc b/riscv/execute.cc index a6ea7a4..ea4dc5b 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -337,6 +337,10 @@ void processor_t::step(size_t n) abort(); } } + catch(trap_debug_mode&) + { + enter_debug_mode(DCSR_CAUSE_SWBP); + } catch (wait_for_interrupt_t &t) { // Return to the outer simulation loop, which gives other devices/harts a -- cgit v1.1 From 7e9da9966856743fb17c42a0a2c2c915e3a3e2b9 Mon Sep 17 00:00:00 2001 From: Kip Walker Date: Wed, 1 Jun 2022 10:51:57 -0700 Subject: Remove the now-unused PC_SERIALIZE_WFI When WFI was changed to throw a C++ exception, the special-npc signaling became obsolete. --- riscv/execute.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'riscv/execute.cc') diff --git a/riscv/execute.cc b/riscv/execute.cc index ea4dc5b..7cb16dd 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -242,7 +242,6 @@ void processor_t::step(size_t n) switch (pc) { \ case PC_SERIALIZE_BEFORE: state.serialized = true; break; \ case PC_SERIALIZE_AFTER: ++instret; break; \ - case PC_SERIALIZE_WFI: n = ++instret; break; \ default: abort(); \ } \ pc = state.pc; \ -- cgit v1.1 From 6b28c78b2cfdf562934fd1d65812cc8707f2cc41 Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Sun, 31 Jul 2022 20:38:10 +0800 Subject: Add #ifdef RISCV_ENABLE_COMMITLOG for commitlog related code --- riscv/execute.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'riscv/execute.cc') diff --git a/riscv/execute.cc b/riscv/execute.cc index 7cb16dd..cc0d4c3 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -172,8 +172,10 @@ inline void processor_t::update_histogram(reg_t pc) // function calls. static inline reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch) { +#ifdef RISCV_ENABLE_COMMITLOG commit_log_reset(p); commit_log_stash_privilege(p); +#endif reg_t npc; try { -- cgit v1.1 From 793ffe508a5b81ce27f1baf2c5afb0b58a4236c6 Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Sun, 31 Jul 2022 20:39:47 +0800 Subject: Fix code indentation in processor.cc, interactive.cc, debug_module.h/cc execute.cc, entropy_source.h and v_ext_macros.h --- riscv/execute.cc | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'riscv/execute.cc') diff --git a/riscv/execute.cc b/riscv/execute.cc index cc0d4c3..1f9ddef 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -240,18 +240,18 @@ void processor_t::step(size_t n) mmu_t* _mmu = mmu; #define advance_pc() \ - if (unlikely(invalid_pc(pc))) { \ - switch (pc) { \ - case PC_SERIALIZE_BEFORE: state.serialized = true; break; \ - case PC_SERIALIZE_AFTER: ++instret; break; \ - default: abort(); \ - } \ - pc = state.pc; \ - break; \ - } else { \ - state.pc = pc; \ - instret++; \ - } + if (unlikely(invalid_pc(pc))) { \ + switch (pc) { \ + case PC_SERIALIZE_BEFORE: state.serialized = true; break; \ + case PC_SERIALIZE_AFTER: ++instret; break; \ + default: abort(); \ + } \ + pc = state.pc; \ + break; \ + } else { \ + state.pc = pc; \ + instret++; \ + } try { -- cgit v1.1 From da93bdc435b985fd354e01c26470f64c33cecaa6 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 22 Sep 2022 15:31:08 -0700 Subject: Delete functions that are actually unused --- riscv/execute.cc | 4 ---- 1 file changed, 4 deletions(-) (limited to 'riscv/execute.cc') diff --git a/riscv/execute.cc b/riscv/execute.cc index 1f9ddef..36621ca 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -154,10 +154,6 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn) } fprintf(log_file, "\n"); } -#else -static void commit_log_reset(processor_t* p) {} -static void commit_log_stash_privilege(processor_t* p) {} -static void commit_log_print_insn(processor_t* p, reg_t pc, insn_t insn) {} #endif inline void processor_t::update_histogram(reg_t pc) -- cgit v1.1 From ce69fb5db97ecf240336b7826dd9dddeb32e5dca Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 22 Sep 2022 17:34:33 -0700 Subject: Suppress most unused variable warnings --- riscv/execute.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'riscv/execute.cc') diff --git a/riscv/execute.cc b/riscv/execute.cc index 36621ca..5d24ce8 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -156,7 +156,7 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn) } #endif -inline void processor_t::update_histogram(reg_t pc) +inline void processor_t::update_histogram(reg_t UNUSED pc) { #ifdef RISCV_ENABLE_HISTOGRAM pc_histogram[pc]++; -- cgit v1.1 From 7b8114f707a7b2de9fd2d393b9d019180de83025 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 6 Oct 2022 17:40:41 -0700 Subject: Don't use reexecution as the means to implement trigger-after The scheme was based on the notion that memory accesses are idempotent up until the point the trigger would've been hit, which isn't true in the case of side-effecting loads and data-value triggers. Instead, check the trigger on the next instruction fetch. To keep the perf overhead minimal, perform this check on the I$ refill path, and ensure that path is taken by flushing the I$. --- riscv/execute.cc | 9 --------- 1 file changed, 9 deletions(-) (limited to 'riscv/execute.cc') diff --git a/riscv/execute.cc b/riscv/execute.cc index 5d24ce8..f0bb946 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -309,15 +309,6 @@ void processor_t::step(size_t n) catch (triggers::matched_t& t) { if (mmu->matched_trigger) { - // This exception came from the MMU. That means the instruction hasn't - // fully executed yet. We start it again, but this time it won't throw - // an exception because matched_trigger is already set. (All memory - // instructions are idempotent so restarting is safe.) - - insn_fetch_t fetch = mmu->load_insn(pc); - pc = execute_insn(this, pc, fetch); - advance_pc(); - delete mmu->matched_trigger; mmu->matched_trigger = NULL; } -- cgit v1.1