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| author | Bruce Hoult <bruce@hoult.org> | 2019-01-21 21:26:23 -0800 |
|---|---|---|
| committer | Bruce Hoult <bruce@hoult.org> | 2019-01-21 21:26:23 -0800 |
| commit | f04f29d352d413d2bc1ed1c7f60319461746540a (patch) | |
| tree | 6f77099e5ea22f947d0627589135b55ff60cc0ab /riscv/debug_module.cc | |
| parent | 412533927340891f3e4d45bed7c3d5ad5d888230 (diff) | |
| download | spike-f04f29d352d413d2bc1ed1c7f60319461746540a.zip spike-f04f29d352d413d2bc1ed1c7f60319461746540a.tar.gz spike-f04f29d352d413d2bc1ed1c7f60319461746540a.tar.bz2 | |
Add FLH and FSH instructions expanding IEEE fp16 in memory to fp32 in registers
Diffstat (limited to 'riscv/debug_module.cc')
| -rw-r--r-- | riscv/debug_module.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index 1972542..f662f42 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -577,6 +577,9 @@ bool debug_module_t::perform_abstract_command() if (write) { switch (size) { + case 1: + write32(debug_abstract, i++, flh(fprnum, ZERO, debug_data_start)); + break; case 2: write32(debug_abstract, i++, flw(fprnum, ZERO, debug_data_start)); break; @@ -590,6 +593,9 @@ bool debug_module_t::perform_abstract_command() } else { switch (size) { + case 1: + write32(debug_abstract, i++, fsh(fprnum, ZERO, debug_data_start)); + break; case 2: write32(debug_abstract, i++, fsw(fprnum, ZERO, debug_data_start)); break; |