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| author | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
| commit | 68aeeb5500521ff52c216862f9a653b64191f3ad (patch) | |
| tree | 407230ff48f79f177a792451598d9b2b6e3d34a0 /riscv/cachesim.h | |
| parent | 191634d2854dfed448fc323195f9b65c305e2d77 (diff) | |
| parent | 03be4ae6c7b8e9865083b61427ff9724c7706fcf (diff) | |
| download | spike-plic_uart_v1.zip spike-plic_uart_v1.tar.gz spike-plic_uart_v1.tar.bz2 | |
Merge branch 'master' into plic_uart_v1plic_uart_v1
Diffstat (limited to 'riscv/cachesim.h')
| -rw-r--r-- | riscv/cachesim.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/riscv/cachesim.h b/riscv/cachesim.h index b7f9014..d7046f9 100644 --- a/riscv/cachesim.h +++ b/riscv/cachesim.h @@ -4,6 +4,7 @@ #define _RISCV_CACHE_SIM_H #include "memtracer.h" +#include "common.h" #include <cstring> #include <string> #include <map> @@ -108,7 +109,7 @@ class icache_sim_t : public cache_memtracer_t { public: icache_sim_t(const char* config) : cache_memtracer_t(config, "I$") {} - bool interested_in_range(uint64_t begin, uint64_t end, access_type type) + bool interested_in_range(uint64_t UNUSED begin, uint64_t UNUSED end, access_type type) { return type == FETCH; } @@ -122,7 +123,7 @@ class dcache_sim_t : public cache_memtracer_t { public: dcache_sim_t(const char* config) : cache_memtracer_t(config, "D$") {} - bool interested_in_range(uint64_t begin, uint64_t end, access_type type) + bool interested_in_range(uint64_t UNUSED begin, uint64_t UNUSED end, access_type type) { return type == LOAD || type == STORE; } |