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| author | Andrew Waterman <andrew@sifive.com> | 2019-03-30 15:09:15 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-05-14 01:50:01 -0700 |
| commit | fd72b8b761d3a404792397d7ccaf20fd11c2470a (patch) | |
| tree | da6a08dcccdf227e3167f8e8650d0810f1c0977c | |
| parent | 6912d1eb40953ab57e9c453e52ecd2e5f3090cbf (diff) | |
| download | spike-fd72b8b761d3a404792397d7ccaf20fd11c2470a.zip spike-fd72b8b761d3a404792397d7ccaf20fd11c2470a.tar.gz spike-fd72b8b761d3a404792397d7ccaf20fd11c2470a.tar.bz2 | |
RV32Q is not invalid
| -rw-r--r-- | riscv/processor.cc | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 3c201b7..3da6504 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -180,12 +180,6 @@ void processor_t::parse_isa_string(const char* str) if (supports_extension('Q') && !supports_extension('D')) bad_isa_string(str); - if (supports_extension('Q') && supports_extension('V')) - bad_isa_string(str); - - if (supports_extension('Q') && max_xlen < 64) - bad_isa_string(str); - max_isa = state.misa; } |