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| author | Dave.Wen <dave.wen@sifive.com> | 2020-05-27 02:23:38 -0700 |
|---|---|---|
| committer | Dave.Wen <dave.wen@sifive.com> | 2020-05-27 02:23:38 -0700 |
| commit | e8a298e2ff8d0c785bb8986d454333e7bd9f4ea3 (patch) | |
| tree | 5b294fb3d69405eac4c7e3a03614385ac19dbfc5 | |
| parent | 443e40537a056309fb000265b26363d08d09c18b (diff) | |
| download | spike-e8a298e2ff8d0c785bb8986d454333e7bd9f4ea3.zip spike-e8a298e2ff8d0c785bb8986d454333e7bd9f4ea3.tar.gz spike-e8a298e2ff8d0c785bb8986d454333e7bd9f4ea3.tar.bz2 | |
rvv: v[z|s]ext: remove redundant requires
| -rw-r--r-- | riscv/decode.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index c1fed9b..981f65e 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1746,8 +1746,6 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ // vector: sign/unsiged extension #define VI_VV_EXT(div, type) \ require(insn.rd() != insn.rs2()); \ - require_align(insn.rd(), P.VU.vflmul); \ - require_align(insn.rs2(), P.VU.vflmul); \ require_vm; \ reg_t from = P.VU.vsew / div; \ require(from >= e8 && from <= e64); \ |