rvv: leave only SEW-bit segment store

new features in spec 0.9

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

17 files changed, 53 insertions, 153 deletions

diff --git a/riscv/decode.h b/riscv/decode.h
index 36fea27..0336d92 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -1561,11 +1561,11 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
   if (nf >= 2) \
     require(!is_overlapped(vd, nf, insn.rs2(), 1));
 
-#define VI_ST(stride, offset, st_width, elt_byte) \
+#define VI_ST(stride, offset, st_width, elt_byte, is_seg) \
   VI_CHECK_STORE_SXX; \
   VI_ST_COMMON(stride, offset, st_width, elt_byte) \
 
-#define VI_ST_INDEX(stride, offset, st_width, elt_byte) \
+#define VI_ST_INDEX(stride, offset, st_width, elt_byte, is_seg) \
   VI_CHECK_ST_INDEX; \
   VI_ST_COMMON(stride, offset, st_width, elt_byte) \
 
diff --git a/riscv/insns/vsb_v.h b/riscv/insns/vsb_v.h
index d8c9090..c5830cc 100644
--- a/riscv/insns/vsb_v.h
+++ b/riscv/insns/vsb_v.h
@@ -1,3 +1,3 @@
-// vsb.v and vsseg[2-8]b.v
+// vsb.v
 require(P.VU.vsew >= e8);
-VI_ST(0, i * nf + fn, uint8, 1);
+VI_ST(0, i * nf + fn, uint8, 1, false);
diff --git a/riscv/insns/vse_v.h b/riscv/insns/vse_v.h
index 1e0dac3..bcb1b21 100644
--- a/riscv/insns/vse_v.h
+++ b/riscv/insns/vse_v.h
@@ -1,13 +1,13 @@
-// vsw.v and vsseg[2-8]w.v
+// vse.v and vsseg[2-8]e.v
 reg_t sew = P.VU.vsew;
 
 if (sew == e8) {
-  VI_ST(0, (i * nf + fn), uint8, 1);
+  VI_ST(0, (i * nf + fn), uint8,  1, true);
 } else if (sew == e16) {
-  VI_ST(0, (i * nf + fn), uint16, 2);
+  VI_ST(0, (i * nf + fn), uint16, 2, true);
 } else if (sew == e32) {
-  VI_ST(0, (i * nf + fn), uint32, 4);
+  VI_ST(0, (i * nf + fn), uint32, 4, true);
 } else if (sew == e64) {
-  VI_ST(0, (i * nf + fn), uint64, 8);
+  VI_ST(0, (i * nf + fn), uint64, 8, true);
 }
 
diff --git a/riscv/insns/vsh_v.h b/riscv/insns/vsh_v.h
index a38bc90..559c93e 100644
--- a/riscv/insns/vsh_v.h
+++ b/riscv/insns/vsh_v.h
@@ -1,3 +1,3 @@
-// vsh.v and vsseg[2-8]h.v
+// vsh.v
 require(P.VU.vsew >= e16);
-VI_ST(0, i * nf + fn, uint16, 2);
+VI_ST(0, i * nf + fn, uint16, 2, false);
diff --git a/riscv/insns/vssb_v.h b/riscv/insns/vssb_v.h
index 1bf0ecf..337b7c0 100644
--- a/riscv/insns/vssb_v.h
+++ b/riscv/insns/vssb_v.h
@@ -1,3 +1,3 @@
-// vssb.v and vssseg[2-8]b.v
+// vssb.v
 require(P.VU.vsew >= e8);
-VI_ST(i * RS2, fn, uint8, 1);
+VI_ST(i * RS2, fn, uint8, 1, false);
diff --git a/riscv/insns/vsse_v.h b/riscv/insns/vsse_v.h
index 2242759..59848dc 100644
--- a/riscv/insns/vsse_v.h
+++ b/riscv/insns/vsse_v.h
@@ -2,12 +2,12 @@
 reg_t sew = P.VU.vsew;
 
 if (sew == e8) {
-  VI_ST(i * RS2, fn, uint8, 1);
+  VI_ST(i * RS2, fn, uint8,  1, false);
 } else if (sew == e16) {
-  VI_ST(i * RS2, fn, uint16, 2);
+  VI_ST(i * RS2, fn, uint16, 2, false);
 } else if (sew == e32) {
-  VI_ST(i * RS2, fn, uint32, 4);
+  VI_ST(i * RS2, fn, uint32, 4, false);
 } else if (sew == e64) {
-  VI_ST(i * RS2, fn, uint64, 8);
+  VI_ST(i * RS2, fn, uint64, 8, false);
 }
 
diff --git a/riscv/insns/vssh_v.h b/riscv/insns/vssh_v.h
index e0ebed2..fcdcbda 100644
--- a/riscv/insns/vssh_v.h
+++ b/riscv/insns/vssh_v.h
@@ -1,3 +1,3 @@
-// vssh.v and vssseg[2-8]h.v
+// vssh.v
 require(P.VU.vsew >= e16);
-VI_ST(i * RS2, fn, uint16, 2);
+VI_ST(i * RS2, fn, uint16, 2, false);
diff --git a/riscv/insns/vssw_v.h b/riscv/insns/vssw_v.h
index c191d2e..ceae158 100644
--- a/riscv/insns/vssw_v.h
+++ b/riscv/insns/vssw_v.h
@@ -1,3 +1,3 @@
-// vssw.v and vssseg[2-8]w.v
+// vssw.v
 require(P.VU.vsew >= e32);
-VI_ST(i * RS2, fn, uint32, 4);
+VI_ST(i * RS2, fn, uint32, 4, false);
diff --git a/riscv/insns/vsuxb_v.h b/riscv/insns/vsuxb_v.h
index 691fb1b..779d37d 100644
--- a/riscv/insns/vsuxb_v.h
+++ b/riscv/insns/vsuxb_v.h
@@ -1,34 +1,4 @@
-// vsuxb.v and vsxseg[2-8]b.v
+// vsuxb.v
 require(P.VU.vsew >= e8);
-VI_CHECK_STORE_SXX;
-require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \
-reg_t vl = P.VU.vl;
-reg_t baseAddr = RS1;
-reg_t stride = insn.rs2();
-reg_t vs3 = insn.rd();
-reg_t vlmax = P.VU.vlmax;
-VI_DUPLICATE_VREG(stride, vlmax);
-for (reg_t i = 0; i < vlmax && vl != 0; ++i) {
-  VI_ELEMENT_SKIP(i);
-  VI_STRIP(i)
-
-  switch (P.VU.vsew) {
-  case e8:
-    MMU.store_uint8(baseAddr + index[i],
-                    P.VU.elt<uint8_t>(vs3, vreg_inx));
-    break;
-  case e16:
-    MMU.store_uint8(baseAddr + index[i],
-                    P.VU.elt<uint16_t>(vs3, vreg_inx));
-    break;
-  case e32:
-    MMU.store_uint8(baseAddr + index[i],
-                    P.VU.elt<uint32_t>(vs3, vreg_inx));
-    break;
-  case e64:
-    MMU.store_uint8(baseAddr + index[i],
-                    P.VU.elt<uint64_t>(vs3, vreg_inx));
-    break;
-  }
-}
-P.VU.vstart = 0;
+VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
+VI_ST_INDEX(index[i], fn, uint8, 1, false);
diff --git a/riscv/insns/vsuxe_v.h b/riscv/insns/vsuxe_v.h
index 438ca6a..1434876 100644
--- a/riscv/insns/vsuxe_v.h
+++ b/riscv/insns/vsuxe_v.h
@@ -1,35 +1,13 @@
-// vsxe.v and vsxseg[2-8]e.v
-const reg_t sew = P.VU.vsew;
-const reg_t vl = P.VU.vl;
+// vsuxe.v
+reg_t sew = P.VU.vsew;
 require(sew >= e8 && sew <= e64);
-VI_CHECK_STORE_SXX;
-require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \
-reg_t baseAddr = RS1;
-reg_t stride = insn.rs2();
-reg_t vs3 = insn.rd();
-reg_t vlmax = P.VU.vlmax;
-VI_DUPLICATE_VREG(stride, vlmax);
-for (reg_t i = 0; i < vlmax && vl != 0; ++i) {
-  VI_ELEMENT_SKIP(i);
-  VI_STRIP(i)
-
-  switch (sew) {
-  case e8:
-    MMU.store_uint8(baseAddr + index[i],
-                    P.VU.elt<uint8_t>(vs3, vreg_inx));
-    break;
-  case e16:
-    MMU.store_uint16(baseAddr + index[i],
-                     P.VU.elt<uint16_t>(vs3, vreg_inx));
-    break;
-  case e32:
-    MMU.store_uint32(baseAddr + index[i],
-                     P.VU.elt<uint32_t>(vs3, vreg_inx));
-    break;
-  case e64:
-    MMU.store_uint64(baseAddr + index[i],
-                     P.VU.elt<uint64_t>(vs3, vreg_inx));
-    break;
-  }
+VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
+if (sew == e8) {
+  VI_ST_INDEX(index[i], fn, uint8,  1, false);
+} else if (sew == e16) {
+  VI_ST_INDEX(index[i], fn, uint16, 2, false);
+} else if (sew == e32) {
+  VI_ST_INDEX(index[i], fn, uint32, 4, false);
+} else if (sew == e64) {
+  VI_ST_INDEX(index[i], fn, uint64, 8, false);
 }
-P.VU.vstart = 0;
diff --git a/riscv/insns/vsuxh_v.h b/riscv/insns/vsuxh_v.h
index 28d2d91..ac89fd9 100644
--- a/riscv/insns/vsuxh_v.h
+++ b/riscv/insns/vsuxh_v.h
@@ -1,30 +1,4 @@
-// vsxh.v and vsxseg[2-8]h.v
+// vsuxh.v
 require(P.VU.vsew >= e16);
-VI_CHECK_STORE_SXX;
-require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \
-reg_t vl = P.VU.vl;
-reg_t baseAddr = RS1;
-reg_t stride = insn.rs2();
-reg_t vs3 = insn.rd();
-reg_t vlmax = P.VU.vlmax;
-VI_DUPLICATE_VREG(stride, vlmax);
-for (reg_t i = 0; i < vlmax && vl != 0; ++i) {
-  VI_ELEMENT_SKIP(i);
-  VI_STRIP(i)
-
-  switch (P.VU.vsew) {
-  case e16:
-    MMU.store_uint16(baseAddr + index[i],
-                     P.VU.elt<uint16_t>(vs3, vreg_inx));
-    break;
-  case e32:
-    MMU.store_uint16(baseAddr + index[i],
-                     P.VU.elt<uint32_t>(vs3, vreg_inx));
-    break;
-  case e64:
-    MMU.store_uint16(baseAddr + index[i],
-                     P.VU.elt<uint64_t>(vs3, vreg_inx));
-    break;
-  }
-}
-P.VU.vstart = 0;
+VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
+VI_ST_INDEX(index[i], fn, uint16, 2, false);
diff --git a/riscv/insns/vsuxw_v.h b/riscv/insns/vsuxw_v.h
index 0ee1f4b..4787c29 100644
--- a/riscv/insns/vsuxw_v.h
+++ b/riscv/insns/vsuxw_v.h
@@ -1,26 +1,4 @@
-// vsxw.v and vsxseg[2-8]w.v
+// vsuxw.v
 require(P.VU.vsew >= e32);
-VI_CHECK_STORE_SXX;
-require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \
-reg_t vl = P.VU.vl;
-reg_t baseAddr = RS1;
-reg_t stride = insn.rs2();
-reg_t vs3 = insn.rd();
-reg_t vlmax = P.VU.vlmax;
-VI_DUPLICATE_VREG(stride, vlmax);
-for (reg_t i = 0; i < vlmax && vl != 0; ++i) {
-  VI_ELEMENT_SKIP(i);
-  VI_STRIP(i)
-
-  switch (P.VU.vsew) {
-  case e32:
-    MMU.store_uint32(baseAddr + index[i],
-                     P.VU.elt<uint32_t>(vs3, vreg_inx));
-    break;
-  case e64:
-    MMU.store_uint32(baseAddr + index[i],
-                     P.VU.elt<uint64_t>(vs3, vreg_inx));
-    break;
-  }
-}
-P.VU.vstart = 0;
+VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
+VI_ST_INDEX(index[i], fn, uint32, 4, false);
diff --git a/riscv/insns/vsw_v.h b/riscv/insns/vsw_v.h
index 5066657..62b816a 100644
--- a/riscv/insns/vsw_v.h
+++ b/riscv/insns/vsw_v.h
@@ -1,3 +1,3 @@
-// vsw.v and vsseg[2-8]w.v
+// vsw.v
 require(P.VU.vsew >= e32);
-VI_ST(0, i * nf + fn, uint32, 4);
+VI_ST(0, i * nf + fn, uint32, 4, false);
diff --git a/riscv/insns/vsxb_v.h b/riscv/insns/vsxb_v.h
index 3ee421c..aa8ca71 100644
--- a/riscv/insns/vsxb_v.h
+++ b/riscv/insns/vsxb_v.h
@@ -1,4 +1,4 @@
-// vsxb.v and vsxseg[2-8]b.v
+// vsxb.v
 require(P.VU.vsew >= e8);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
-VI_ST_INDEX(index[i], fn, uint8, 1);
+VI_ST_INDEX(index[i], fn, uint8, 1, false);
diff --git a/riscv/insns/vsxe_v.h b/riscv/insns/vsxe_v.h
index 8e5d6e7..d4b2457 100644
--- a/riscv/insns/vsxe_v.h
+++ b/riscv/insns/vsxe_v.h
@@ -3,12 +3,12 @@ reg_t sew = P.VU.vsew;
 require(sew >= e8 && sew <= e64);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
 if (sew == e8) {
-  VI_ST_INDEX(index[i], fn, uint8, 1);
+  VI_ST_INDEX(index[i], fn, uint8,  1, true);
 } else if (sew == e16) {
-  VI_ST_INDEX(index[i], fn, uint16, 2);
+  VI_ST_INDEX(index[i], fn, uint16, 2, true);
 } else if (sew == e32) {
-  VI_ST_INDEX(index[i], fn, uint32, 4);
+  VI_ST_INDEX(index[i], fn, uint32, 4, true);
 } else if (sew == e64) {
-  VI_ST_INDEX(index[i], fn, uint64, 8);
+  VI_ST_INDEX(index[i], fn, uint64, 8, true);
 }
 
diff --git a/riscv/insns/vsxh_v.h b/riscv/insns/vsxh_v.h
index 8722fdc..5f292f8 100644
--- a/riscv/insns/vsxh_v.h
+++ b/riscv/insns/vsxh_v.h
@@ -1,4 +1,4 @@
-// vsxh.v and vsxseg[2-8]h.v
+// vsxh.v
 require(P.VU.vsew >= e16);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
-VI_ST_INDEX(index[i], fn, uint16, 2);
+VI_ST_INDEX(index[i], fn, uint16, 2, false);
diff --git a/riscv/insns/vsxw_v.h b/riscv/insns/vsxw_v.h
index a6d4046..029347f 100644
--- a/riscv/insns/vsxw_v.h
+++ b/riscv/insns/vsxw_v.h
@@ -1,4 +1,4 @@
-// vsxw.v and vsxseg[2-8]w.v
+// vsxw.v
 require(P.VU.vsew >= e32);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
-VI_ST_INDEX(index[i], fn, uint32, 4);
+VI_ST_INDEX(index[i], fn, uint32, 4, false);