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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-22 00:36:40 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-22 18:51:05 -0700 |
| commit | baf160fa42d3f112100b36f6831dbbcbda143336 (patch) | |
| tree | c96e500ecbb030c9eea52302818918e1ec807196 | |
| parent | 056cbfd7fa5a47191812dfef9aeb3b63159e1f22 (diff) | |
| download | spike-baf160fa42d3f112100b36f6831dbbcbda143336.zip spike-baf160fa42d3f112100b36f6831dbbcbda143336.tar.gz spike-baf160fa42d3f112100b36f6831dbbcbda143336.tar.bz2 | |
rvv: fix segment load/store nf checking
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/decode.h | 12 | ||||
| -rw-r--r-- | riscv/insns/vsse_v.h | 8 |
2 files changed, 11 insertions, 9 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index f9c3bc8..cce9f04 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1494,13 +1494,15 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \ } \ } -#define VI_ST_COMMON(stride, offset, st_width, elt_byte) \ +#define VI_ST_COMMON(stride, offset, st_width, elt_byte, is_seg) \ const reg_t nf = insn.v_nf() + 1; \ const reg_t vl = P.VU.vl; \ const reg_t baseAddr = RS1; \ const reg_t vs3 = insn.rd(); \ require((nf * P.VU.vlmul) <= (NVPR / 4) && \ vs3 + nf * P.VU.vlmul <= NVPR); \ + if (!is_seg) \ + require(nf == 1); \ const reg_t vlmul = P.VU.vlmul; \ for (reg_t i = 0; i < vl; ++i) { \ VI_STRIP(i) \ @@ -1527,7 +1529,7 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \ P.VU.vstart = 0; #define VI_LD_COMMON(stride, offset, ld_width, elt_byte, is_seg) \ - const reg_t nf = is_seg ? insn.v_nf() + 1 : 1; \ + const reg_t nf = insn.v_nf() + 1; \ const reg_t vl = P.VU.vl; \ const reg_t baseAddr = RS1; \ const reg_t vd = insn.rd(); \ @@ -1571,15 +1573,15 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \ #define VI_ST(stride, offset, st_width, elt_byte, is_seg) \ VI_CHECK_STORE_SXX; \ - VI_ST_COMMON(stride, offset, st_width, elt_byte) \ + VI_ST_COMMON(stride, offset, st_width, elt_byte, is_seg) \ #define VI_ST_INDEX(stride, offset, st_width, elt_byte, is_seg) \ VI_CHECK_ST_INDEX; \ - VI_ST_COMMON(stride, offset, st_width, elt_byte) \ + VI_ST_COMMON(stride, offset, st_width, elt_byte, is_seg) \ #define VI_LDST_FF(itype, tsew, is_seg) \ require(p->VU.vsew >= e##tsew && p->VU.vsew <= e64); \ - const reg_t nf = is_seg ? insn.v_nf() + 1 : 1; \ + const reg_t nf = insn.v_nf() + 1; \ require((nf * P.VU.vlmul) <= (NVPR / 4)); \ if (!is_seg) \ require(nf == 1); \ diff --git a/riscv/insns/vsse_v.h b/riscv/insns/vsse_v.h index 59848dc..a682e2b 100644 --- a/riscv/insns/vsse_v.h +++ b/riscv/insns/vsse_v.h @@ -2,12 +2,12 @@ reg_t sew = P.VU.vsew; if (sew == e8) { - VI_ST(i * RS2, fn, uint8, 1, false); + VI_ST(i * RS2, fn, uint8, 1, true); } else if (sew == e16) { - VI_ST(i * RS2, fn, uint16, 2, false); + VI_ST(i * RS2, fn, uint16, 2, true); } else if (sew == e32) { - VI_ST(i * RS2, fn, uint32, 4, false); + VI_ST(i * RS2, fn, uint32, 4, true); } else if (sew == e64) { - VI_ST(i * RS2, fn, uint64, 8, false); + VI_ST(i * RS2, fn, uint64, 8, true); } |