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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-15 19:51:00 -0700 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-16 10:01:59 -0700 |
commit | a5c8c5f5e2c88b438bfbd5ee00a058db31a42a40 (patch) | |
tree | 93ee9c3498b2ec37a3edeb6360628d807fce8d66 | |
parent | ddc056fe783ed74f3770ecb4d3d08dc3ecb2495a (diff) | |
download | spike-a5c8c5f5e2c88b438bfbd5ee00a058db31a42a40.zip spike-a5c8c5f5e2c88b438bfbd5ee00a058db31a42a40.tar.gz spike-a5c8c5f5e2c88b438bfbd5ee00a058db31a42a40.tar.bz2 |
rvv: fix rtz cvt
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
-rw-r--r-- | riscv/insns/vfcvt_f_x_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vfcvt_f_xu_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vfcvt_rtz_x_f_v.h | 13 | ||||
-rw-r--r-- | riscv/insns/vfcvt_rtz_xu_f_v.h | 14 | ||||
-rw-r--r-- | riscv/insns/vfcvt_x_f_v.h | 3 | ||||
-rw-r--r-- | riscv/insns/vfcvt_xu_f_v.h | 3 | ||||
-rw-r--r-- | riscv/insns/vfncvt_rod_f_f_w.h | 2 | ||||
-rw-r--r-- | riscv/insns/vfncvt_rtz_x_f_w.h | 20 | ||||
-rw-r--r-- | riscv/insns/vfncvt_rtz_xu_f_w.h | 20 | ||||
-rw-r--r-- | riscv/insns/vfncvt_x_f_w.h | 5 | ||||
-rw-r--r-- | riscv/insns/vfncvt_xu_f_w.h | 2 | ||||
-rw-r--r-- | riscv/insns/vfwcvt_rtz_x_f_v.h | 6 | ||||
-rw-r--r-- | riscv/insns/vfwcvt_rtz_xu_f_v.h | 6 | ||||
-rw-r--r-- | spike_main/disasm.cc | 4 |
14 files changed, 49 insertions, 53 deletions
diff --git a/riscv/insns/vfcvt_f_x_v.h b/riscv/insns/vfcvt_f_x_v.h index dc8363c..c53b0e1 100644 --- a/riscv/insns/vfcvt_f_x_v.h +++ b/riscv/insns/vfcvt_f_x_v.h @@ -1,7 +1,7 @@ // vfcvt.f.x.v vd, vd2, vm VI_VFP_VF_LOOP ({ - auto vs2_i = P.VU.elt<int32_t>(rs2_num, i); + auto vs2_i = P.VU.elt<int16_t>(rs2_num, i); vd = i32_to_f16(vs2_i); }, { diff --git a/riscv/insns/vfcvt_f_xu_v.h b/riscv/insns/vfcvt_f_xu_v.h index 8619aa2..bd03768 100644 --- a/riscv/insns/vfcvt_f_xu_v.h +++ b/riscv/insns/vfcvt_f_xu_v.h @@ -1,7 +1,7 @@ // vfcvt.f.xu.v vd, vd2, vm VI_VFP_VF_LOOP ({ - auto vs2_u = P.VU.elt<uint32_t>(rs2_num, i); + auto vs2_u = P.VU.elt<uint16_t>(rs2_num, i); vd = ui32_to_f16(vs2_u); }, { diff --git a/riscv/insns/vfcvt_rtz_x_f_v.h b/riscv/insns/vfcvt_rtz_x_f_v.h index 5493b09..165ac8d 100644 --- a/riscv/insns/vfcvt_rtz_x_f_v.h +++ b/riscv/insns/vfcvt_rtz_x_f_v.h @@ -1,14 +1,13 @@ -// vfcvt.x.f.v vd, vd2, vm +// vfcvt.rtz.x.f.v vd, vd2, vm VI_VFP_VF_LOOP ({ - softfloat_roundingMode = softfloat_round_minMag; - P.VU.elt<int16_t>(rd_num, i) = f16_to_i32(vs2, STATE.frm, true); + require(0); + //P.VU.elt<int16_t>(rd_num, i) = f16_to_i16(vs2, softfloat_round_minMag, true); }, { - softfloat_roundingMode = softfloat_round_minMag; - P.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, STATE.frm, true); + P.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, softfloat_round_minMag, true); + fprintf(stderr, "here 1: %lx\n", i); }, { - softfloat_roundingMode = softfloat_round_minMag; - P.VU.elt<int64_t>(rd_num, i) = f64_to_i64(vs2, STATE.frm, true); + P.VU.elt<int64_t>(rd_num, i) = f64_to_i64(vs2, softfloat_round_minMag, true); }) diff --git a/riscv/insns/vfcvt_rtz_xu_f_v.h b/riscv/insns/vfcvt_rtz_xu_f_v.h index 0359b81..368d5e1 100644 --- a/riscv/insns/vfcvt_rtz_xu_f_v.h +++ b/riscv/insns/vfcvt_rtz_xu_f_v.h @@ -1,14 +1,12 @@ -// vfcvt.xu.f.v vd, vd2, vm -VI_VFP_VV_LOOP +// vfcvt.rtz.xu.f.v vd, vd2, vm +VI_VFP_VF_LOOP ({ - softfloat_roundingMode = softfloat_round_minMag; - P.VU.elt<uint16_t>(rd_num, i) = f16_to_ui32(vs2, STATE.frm, true); + require(0); + //P.VU.elt<uint16_t>(rd_num, i) = f16_to_ui16(vs2, softfloat_round_minMag, true); }, { - softfloat_roundingMode = softfloat_round_minMag; - P.VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, STATE.frm, true); + P.VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, softfloat_round_minMag, true); }, { - softfloat_roundingMode = softfloat_round_minMag; - P.VU.elt<uint64_t>(rd_num, i) = f64_to_ui64(vs2, STATE.frm, true); + P.VU.elt<uint64_t>(rd_num, i) = f64_to_ui64(vs2, softfloat_round_minMag, true); }) diff --git a/riscv/insns/vfcvt_x_f_v.h b/riscv/insns/vfcvt_x_f_v.h index 2ce19fc..153afbc 100644 --- a/riscv/insns/vfcvt_x_f_v.h +++ b/riscv/insns/vfcvt_x_f_v.h @@ -1,7 +1,8 @@ // vfcvt.x.f.v vd, vd2, vm VI_VFP_VF_LOOP ({ - P.VU.elt<int32_t>(rd_num, i) = f16_to_i32(vs2, STATE.frm, true); + require(0); + //P.VU.elt<int16_t>(rd_num, i) = f16_to_i16(vs2, STATE.frm, true); }, { P.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, STATE.frm, true); diff --git a/riscv/insns/vfcvt_xu_f_v.h b/riscv/insns/vfcvt_xu_f_v.h index febe8e2..3f9a31b 100644 --- a/riscv/insns/vfcvt_xu_f_v.h +++ b/riscv/insns/vfcvt_xu_f_v.h @@ -1,7 +1,8 @@ // vfcvt.xu.f.v vd, vd2, vm VI_VFP_VV_LOOP ({ - P.VU.elt<uint32_t>(rd_num, i) = f16_to_ui32(vs2, STATE.frm, true); + require(0); + //P.VU.elt<uint16_t>(rd_num, i) = f16_to_ui16(vs2, STATE.frm, true); }, { P.VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, STATE.frm, true); diff --git a/riscv/insns/vfncvt_rod_f_f_w.h b/riscv/insns/vfncvt_rod_f_f_w.h index 77501e6..864b784 100644 --- a/riscv/insns/vfncvt_rod_f_f_w.h +++ b/riscv/insns/vfncvt_rod_f_f_w.h @@ -1,4 +1,4 @@ -// vfncvt.f.f.v vd, vs2, vm +// vfncvt.rod.f.f.v vd, vs2, vm VI_VFP_CVT_SCALE ({ softfloat_roundingMode = softfloat_round_odd; diff --git a/riscv/insns/vfncvt_rtz_x_f_w.h b/riscv/insns/vfncvt_rtz_x_f_w.h index 3cbc684..7fc841c 100644 --- a/riscv/insns/vfncvt_rtz_x_f_w.h +++ b/riscv/insns/vfncvt_rtz_x_f_w.h @@ -1,11 +1,11 @@ -// vfncvt.x.f.v vd, vs2, vm -VI_CHECK_SDS(false); -if (P.VU.vsew == e32) - require(p->supports_extension('D')); - -VI_VFP_LOOP_BASE - softfloat_roundingMode = softfloat_round_minMag; +// vfncvt.rtz.x.f.w vd, vs2, vm +VI_VFP_CVT_SCALE +({ + require(0); + auto vs2 = P.VU.elt<float32_t>(rs2_num, i); + //P.VU.elt<int16_t>(rd_num, i, true) = f32_to_i16(vs2, softfloat_round_minMag, true); +}, +{ auto vs2 = P.VU.elt<float64_t>(rs2_num, i); - P.VU.elt<int32_t>(rd_num, i, true) = f64_to_i32(vs2, STATE.frm, true); - set_fp_exceptions; -VI_VFP_LOOP_END + P.VU.elt<int32_t>(rd_num, i, true) = f64_to_i32(vs2, softfloat_round_minMag, true); +}, false) diff --git a/riscv/insns/vfncvt_rtz_xu_f_w.h b/riscv/insns/vfncvt_rtz_xu_f_w.h index 4c5e785..470dab2 100644 --- a/riscv/insns/vfncvt_rtz_xu_f_w.h +++ b/riscv/insns/vfncvt_rtz_xu_f_w.h @@ -1,11 +1,11 @@ -// vfncvt.xu.f.v vd, vs2, vm -VI_CHECK_SDS(false); -if (P.VU.vsew == e32) - require(p->supports_extension('D')); - -VI_VFP_LOOP_BASE - softfloat_roundingMode = softfloat_round_minMag; +// vfncvt.rtz.xu.f.w vd, vs2, vm +VI_VFP_CVT_SCALE +({ + require(0); + auto vs2 = P.VU.elt<float32_t>(rs2_num, i); + //P.VU.elt<uint16_t>(rd_num, i, true) = f32_to_ui16(vs2, softfloat_round_minMag, true); +}, +{ auto vs2 = P.VU.elt<float64_t>(rs2_num, i); - P.VU.elt<uint32_t>(rd_num, i, true) = f64_to_ui32(vs2, STATE.frm, true); - set_fp_exceptions; -VI_VFP_LOOP_END + P.VU.elt<uint32_t>(rd_num, i, true) = f64_to_ui32(vs2, softfloat_round_minMag, true); +}, false) diff --git a/riscv/insns/vfncvt_x_f_w.h b/riscv/insns/vfncvt_x_f_w.h index b7a7e42..714b76a 100644 --- a/riscv/insns/vfncvt_x_f_w.h +++ b/riscv/insns/vfncvt_x_f_w.h @@ -1,8 +1,9 @@ -// vfncvt.x.f.v vd, vs2, vm +// vfncvt.x.f.w vd, vs2, vm VI_VFP_CVT_SCALE ({ + require(0); auto vs2 = P.VU.elt<float32_t>(rs2_num, i); - P.VU.elt<int16_t>(rd_num, i, true) = f32_to_i32(vs2, STATE.frm, true); + //P.VU.elt<int16_t>(rd_num, i, true) = f32_to_i16(vs2, STATE.frm, true); }, { auto vs2 = P.VU.elt<float64_t>(rs2_num, i); diff --git a/riscv/insns/vfncvt_xu_f_w.h b/riscv/insns/vfncvt_xu_f_w.h index 0673b35..ad1c3ba 100644 --- a/riscv/insns/vfncvt_xu_f_w.h +++ b/riscv/insns/vfncvt_xu_f_w.h @@ -1,4 +1,4 @@ -// vfncvt.xu.f.v vd, vs2, vm +// vfncvt.xu.f.w vd, vs2, vm VI_VFP_CVT_SCALE ({ auto vs2 = P.VU.elt<float32_t>(rs2_num, i); diff --git a/riscv/insns/vfwcvt_rtz_x_f_v.h b/riscv/insns/vfwcvt_rtz_x_f_v.h index 4c421c8..ad3a90d 100644 --- a/riscv/insns/vfwcvt_rtz_x_f_v.h +++ b/riscv/insns/vfwcvt_rtz_x_f_v.h @@ -1,12 +1,10 @@ // vfwcvt.rtz.x.f.v vd, vs2, vm VI_VFP_CVT_SCALE ({ - softfloat_roundingMode = softfloat_round_minMag; auto vs2 = P.VU.elt<float16_t>(rs2_num, i); - P.VU.elt<int32_t>(rd_num, i, true) = f16_to_i32(vs2, STATE.frm, true); + P.VU.elt<int32_t>(rd_num, i, true) = f16_to_i32(vs2, softfloat_round_minMag, true); }, { - softfloat_roundingMode = softfloat_round_minMag; auto vs2 = P.VU.elt<float32_t>(rs2_num, i); - P.VU.elt<int64_t>(rd_num, i, true) = f32_to_i64(vs2, STATE.frm, true); + P.VU.elt<int64_t>(rd_num, i, true) = f32_to_i64(vs2, softfloat_round_minMag, true); }, true) diff --git a/riscv/insns/vfwcvt_rtz_xu_f_v.h b/riscv/insns/vfwcvt_rtz_xu_f_v.h index 894582d..297008f 100644 --- a/riscv/insns/vfwcvt_rtz_xu_f_v.h +++ b/riscv/insns/vfwcvt_rtz_xu_f_v.h @@ -1,12 +1,10 @@ // vfwcvt.rtz,xu.f.v vd, vs2, vm VI_VFP_CVT_SCALE ({ - softfloat_roundingMode = softfloat_round_minMag; auto vs2 = P.VU.elt<float16_t>(rs2_num, i); - P.VU.elt<uint32_t>(rd_num, i, true) = f16_to_ui32(vs2, STATE.frm, true); + P.VU.elt<uint32_t>(rd_num, i, true) = f16_to_ui32(vs2, softfloat_round_minMag, true); }, { - softfloat_roundingMode = softfloat_round_minMag; auto vs2 = P.VU.elt<float32_t>(rs2_num, i); - P.VU.elt<uint64_t>(rd_num, i, true) = f32_to_ui64(vs2, STATE.frm, true); + P.VU.elt<uint64_t>(rd_num, i, true) = f32_to_ui64(vs2, softfloat_round_minMag, true); }, true) diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc index d8c9eb4..fe6be50 100644 --- a/spike_main/disasm.cc +++ b/spike_main/disasm.cc @@ -990,10 +990,10 @@ disassembler_t::disassembler_t(int xlen) match_##name##cvt_f_x_##suf, mask_##name##cvt_f_x_##suf, \ {&vd, &vs2, &opt, &vm})); \ add_insn(new disasm_insn_t(#name "cvt.rtz.xu.f." #suf, \ - match_##name##cvt_xu_f_##suf, mask_##name##cvt_xu_f_##suf, \ + match_##name##cvt_rtz_xu_f_##suf, mask_##name##cvt_rtz_xu_f_##suf, \ {&vd, &vs2, &opt, &vm})); \ add_insn(new disasm_insn_t(#name "cvt.rtz.x.f." #suf, \ - match_##name##cvt_x_f_##suf, mask_##name##cvt_x_f_##suf, \ + match_##name##cvt_rtz_x_f_##suf, mask_##name##cvt_rtz_x_f_##suf, \ {&vd, &vs2, &opt, &vm})); \ //OPFVV/OPFVF |