diff options
| author | YenHaoChen <howard25336284@gmail.com> | 2024-05-24 09:12:18 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2024-05-24 09:12:21 +0800 |
| commit | 8ad1b68911c2b0c74bc8f00cf7f0f37bceca186e (patch) | |
| tree | 9d145659674e1f18481010e714ce48aabe1fafbf | |
| parent | 2cfd5393520c0673fd0182fcca430351d9e6682d (diff) | |
| download | spike-8ad1b68911c2b0c74bc8f00cf7f0f37bceca186e.zip spike-8ad1b68911c2b0c74bc8f00cf7f0f37bceca186e.tar.gz spike-8ad1b68911c2b0c74bc8f00cf7f0f37bceca186e.tar.bz2 | |
vector: Not logging write of reduction instructions when vl = 0
The spec says: "If vl=0, no operation is performed and the destination
register is not updated." in Section 14. Vector Reduction Operations.
The commit proposes setting the variable is_write to false when vl = 0,
which means not logging the write.
| -rw-r--r-- | riscv/v_ext_macros.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h index 8f9820d..a95af3e 100644 --- a/riscv/v_ext_macros.h +++ b/riscv/v_ext_macros.h @@ -608,7 +608,7 @@ static inline bool is_overlapped_widen(const int astart, int asize, reg_t rd_num = insn.rd(); \ reg_t rs1_num = insn.rs1(); \ reg_t rs2_num = insn.rs2(); \ - auto &vd_0_des = P.VU.elt<type_sew_t<x>::type>(rd_num, 0, true); \ + auto &vd_0_des = P.VU.elt<type_sew_t<x>::type>(rd_num, 0, vl > 0); \ auto vd_0_res = P.VU.elt<type_sew_t<x>::type>(rs1_num, 0); \ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ VI_LOOP_ELEMENT_SKIP(); \ @@ -639,7 +639,7 @@ static inline bool is_overlapped_widen(const int astart, int asize, reg_t rd_num = insn.rd(); \ reg_t rs1_num = insn.rs1(); \ reg_t rs2_num = insn.rs2(); \ - auto &vd_0_des = P.VU.elt<type_usew_t<x>::type>(rd_num, 0, true); \ + auto &vd_0_des = P.VU.elt<type_usew_t<x>::type>(rd_num, 0, vl > 0); \ auto vd_0_res = P.VU.elt<type_usew_t<x>::type>(rs1_num, 0); \ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ VI_LOOP_ELEMENT_SKIP(); \ @@ -1019,7 +1019,7 @@ static inline bool is_overlapped_widen(const int astart, int asize, reg_t rd_num = insn.rd(); \ reg_t rs1_num = insn.rs1(); \ reg_t rs2_num = insn.rs2(); \ - auto &vd_0_des = P.VU.elt<type_sew_t<sew2>::type>(rd_num, 0, true); \ + auto &vd_0_des = P.VU.elt<type_sew_t<sew2>::type>(rd_num, 0, vl > 0); \ auto vd_0_res = P.VU.elt<type_sew_t<sew2>::type>(rs1_num, 0); \ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ VI_LOOP_ELEMENT_SKIP(); \ @@ -1047,7 +1047,7 @@ static inline bool is_overlapped_widen(const int astart, int asize, reg_t rd_num = insn.rd(); \ reg_t rs1_num = insn.rs1(); \ reg_t rs2_num = insn.rs2(); \ - auto &vd_0_des = P.VU.elt<type_usew_t<sew2>::type>(rd_num, 0, true); \ + auto &vd_0_des = P.VU.elt<type_usew_t<sew2>::type>(rd_num, 0, vl > 0); \ auto vd_0_res = P.VU.elt<type_usew_t<sew2>::type>(rs1_num, 0); \ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ VI_LOOP_ELEMENT_SKIP(); \ |