diff options
| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-24 21:06:06 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-24 21:06:06 -0700 |
| commit | 6ace3fa83601cdf6b5e19eea84166b02f9cb88ba (patch) | |
| tree | d519b0af27aaf960446abb22ecad426d8763b9b6 | |
| parent | 18e03d0e515eeb38e7f11cf7bb580df83d51f114 (diff) | |
| download | spike-6ace3fa83601cdf6b5e19eea84166b02f9cb88ba.zip spike-6ace3fa83601cdf6b5e19eea84166b02f9cb88ba.tar.gz spike-6ace3fa83601cdf6b5e19eea84166b02f9cb88ba.tar.bz2 | |
rvv: add missing lmul/vsew/elen checking
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/processor.cc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 9db3f6a..b67c54a 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -391,7 +391,12 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT vma = BITS(newType, 7, 7); vediv = 1 << BITS(newType, 9, 8); - vill = !(vflmul >= 0.125 && vflmul <= 8) || vsew > ELEN || vediv != 1 || (newType >> 8) != 0; + vill = !(vflmul >= 0.125 && vflmul <= 8) + || vsew > ELEN + || vflmul < ((float)vsew / ELEN) + || vediv != 1 + || (newType >> 8) != 0; + if (vill) { vlmax = 0; vtype = UINT64_MAX << (p->get_xlen() - 1); |