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| author | Tim Newsome <tim@sifive.com> | 2016-05-09 14:43:12 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:12 -0700 |
| commit | 5b2c9df0b3db0d504ef2fb2a68f18f91cfcc5966 (patch) | |
| tree | d0e9e92240609119b3dde6c904ed2e3afec9f726 | |
| parent | 060d4ee6c826b3ccdb3d8763246a09b6ef8ce04d (diff) | |
| download | spike-5b2c9df0b3db0d504ef2fb2a68f18f91cfcc5966.zip spike-5b2c9df0b3db0d504ef2fb2a68f18f91cfcc5966.tar.gz spike-5b2c9df0b3db0d504ef2fb2a68f18f91cfcc5966.tar.bz2 | |
Remove already-implemented TODO.
| -rw-r--r-- | riscv/processor.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 87e509d..25b6144 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -380,7 +380,6 @@ void processor_t::set_csr(int which, reg_t val) case CSR_MCAUSE: state.mcause = val; break; case CSR_MBADADDR: state.mbadaddr = val; break; case CSR_DCSR: - // TODO: Use get_field style state.dcsr.prv = get_field(val, DCSR_PRV); state.dcsr.step = get_field(val, DCSR_STEP); // TODO: ndreset and fullreset |