diff options
author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-05-16 17:49:34 -0700 |
---|---|---|
committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-05-16 18:02:42 -0700 |
commit | 28229ac7f04e0ab0b2cb142782adbb656a84715d (patch) | |
tree | ccaf793f2014d0935c3e843b07b3c03ee7787878 | |
parent | 2a990e1764aea73927612f1497e2368c5607b2b2 (diff) | |
download | spike-28229ac7f04e0ab0b2cb142782adbb656a84715d.zip spike-28229ac7f04e0ab0b2cb142782adbb656a84715d.tar.gz spike-28229ac7f04e0ab0b2cb142782adbb656a84715d.tar.bz2 |
rvv: fix integer reduction instruction suffix
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
-rw-r--r-- | riscv/encoding.h | 48 | ||||
-rw-r--r-- | riscv/insns/vredand_vs.h (renamed from riscv/insns/vredand_vv.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vredmax_vs.h (renamed from riscv/insns/vredmax_vv.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vredmaxu_vs.h (renamed from riscv/insns/vredmaxu_vv.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vredmin_vs.h (renamed from riscv/insns/vredmin_vv.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vredminu_vs.h (renamed from riscv/insns/vredminu_vv.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vredor_vs.h (renamed from riscv/insns/vredor_vv.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vredsum_vs.h (renamed from riscv/insns/vredsum_vv.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vredxor_vs.h (renamed from riscv/insns/vredxor_vv.h) | 0 | ||||
-rw-r--r-- | riscv/riscv.mk.in | 17 | ||||
-rw-r--r-- | spike_main/disasm.cc | 16 |
11 files changed, 40 insertions, 41 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index 3acc099..31cbf18 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -1236,22 +1236,22 @@ #define MASK_VNCLIPU_VI 0xfc00707f #define MATCH_VNCLIP_VI 0xbc003057 #define MASK_VNCLIP_VI 0xfc00707f -#define MATCH_VREDSUM_VV 0x2057 -#define MASK_VREDSUM_VV 0xfc00707f -#define MATCH_VREDAND_VV 0x4002057 -#define MASK_VREDAND_VV 0xfc00707f -#define MATCH_VREDOR_VV 0x8002057 -#define MASK_VREDOR_VV 0xfc00707f -#define MATCH_VREDXOR_VV 0xc002057 -#define MASK_VREDXOR_VV 0xfc00707f -#define MATCH_VREDMINU_VV 0x10002057 -#define MASK_VREDMINU_VV 0xfc00707f -#define MATCH_VREDMIN_VV 0x14002057 -#define MASK_VREDMIN_VV 0xfc00707f -#define MATCH_VREDMAXU_VV 0x18002057 -#define MASK_VREDMAXU_VV 0xfc00707f -#define MATCH_VREDMAX_VV 0x1c002057 -#define MASK_VREDMAX_VV 0xfc00707f +#define MATCH_VREDSUM_VS 0x2057 +#define MASK_VREDSUM_VS 0xfc00707f +#define MATCH_VREDAND_VS 0x4002057 +#define MASK_VREDAND_VS 0xfc00707f +#define MATCH_VREDOR_VS 0x8002057 +#define MASK_VREDOR_VS 0xfc00707f +#define MATCH_VREDXOR_VS 0xc002057 +#define MASK_VREDXOR_VS 0xfc00707f +#define MATCH_VREDMINU_VS 0x10002057 +#define MASK_VREDMINU_VS 0xfc00707f +#define MATCH_VREDMIN_VS 0x14002057 +#define MASK_VREDMIN_VS 0xfc00707f +#define MATCH_VREDMAXU_VS 0x18002057 +#define MASK_VREDMAXU_VS 0xfc00707f +#define MATCH_VREDMAX_VS 0x1c002057 +#define MASK_VREDMAX_VS 0xfc00707f #define MATCH_VEXT_X_V 0x30002057 #define MASK_VEXT_X_V 0xfc00707f #define MATCH_VMPOPC_M 0x50002057 @@ -2167,14 +2167,14 @@ DECLARE_INSN(vnsrl_vi, MATCH_VNSRL_VI, MASK_VNSRL_VI) DECLARE_INSN(vnsra_vi, MATCH_VNSRA_VI, MASK_VNSRA_VI) DECLARE_INSN(vnclipu_vi, MATCH_VNCLIPU_VI, MASK_VNCLIPU_VI) DECLARE_INSN(vnclip_vi, MATCH_VNCLIP_VI, MASK_VNCLIP_VI) -DECLARE_INSN(vredsum_vv, MATCH_VREDSUM_VV, MASK_VREDSUM_VV) -DECLARE_INSN(vredand_vv, MATCH_VREDAND_VV, MASK_VREDAND_VV) -DECLARE_INSN(vredor_vv, MATCH_VREDOR_VV, MASK_VREDOR_VV) -DECLARE_INSN(vredxor_vv, MATCH_VREDXOR_VV, MASK_VREDXOR_VV) -DECLARE_INSN(vredminu_vv, MATCH_VREDMINU_VV, MASK_VREDMINU_VV) -DECLARE_INSN(vredmin_vv, MATCH_VREDMIN_VV, MASK_VREDMIN_VV) -DECLARE_INSN(vredmaxu_vv, MATCH_VREDMAXU_VV, MASK_VREDMAXU_VV) -DECLARE_INSN(vredmax_vv, MATCH_VREDMAX_VV, MASK_VREDMAX_VV) +DECLARE_INSN(vredsum_vs, MATCH_VREDSUM_VS, MASK_VREDSUM_VS) +DECLARE_INSN(vredand_vs, MATCH_VREDAND_VS, MASK_VREDAND_VS) +DECLARE_INSN(vredor_vs, MATCH_VREDOR_VS, MASK_VREDOR_VS) +DECLARE_INSN(vredxor_vs, MATCH_VREDXOR_VS, MASK_VREDXOR_VS) +DECLARE_INSN(vredminu_vs, MATCH_VREDMINU_VS, MASK_VREDMINU_VS) +DECLARE_INSN(vredmin_vs, MATCH_VREDMIN_VS, MASK_VREDMIN_VS) +DECLARE_INSN(vredmaxu_vs, MATCH_VREDMAXU_VS, MASK_VREDMAXU_VS) +DECLARE_INSN(vredmax_vs, MATCH_VREDMAX_VS, MASK_VREDMAX_VS) DECLARE_INSN(vext_x_v, MATCH_VEXT_X_V, MASK_VEXT_X_V) DECLARE_INSN(vmpopc_m, MATCH_VMPOPC_M, MASK_VMPOPC_M) DECLARE_INSN(vmfirst_m, MATCH_VMFIRST_M, MASK_VMFIRST_M) diff --git a/riscv/insns/vredand_vv.h b/riscv/insns/vredand_vs.h index 6c2d908..6c2d908 100644 --- a/riscv/insns/vredand_vv.h +++ b/riscv/insns/vredand_vs.h diff --git a/riscv/insns/vredmax_vv.h b/riscv/insns/vredmax_vs.h index be2e76a..be2e76a 100644 --- a/riscv/insns/vredmax_vv.h +++ b/riscv/insns/vredmax_vs.h diff --git a/riscv/insns/vredmaxu_vv.h b/riscv/insns/vredmaxu_vs.h index ca33a95..ca33a95 100644 --- a/riscv/insns/vredmaxu_vv.h +++ b/riscv/insns/vredmaxu_vs.h diff --git a/riscv/insns/vredmin_vv.h b/riscv/insns/vredmin_vs.h index 50359b7..50359b7 100644 --- a/riscv/insns/vredmin_vv.h +++ b/riscv/insns/vredmin_vs.h diff --git a/riscv/insns/vredminu_vv.h b/riscv/insns/vredminu_vs.h index bfb77e6..bfb77e6 100644 --- a/riscv/insns/vredminu_vv.h +++ b/riscv/insns/vredminu_vs.h diff --git a/riscv/insns/vredor_vv.h b/riscv/insns/vredor_vs.h index f7acd9a..f7acd9a 100644 --- a/riscv/insns/vredor_vv.h +++ b/riscv/insns/vredor_vs.h diff --git a/riscv/insns/vredsum_vv.h b/riscv/insns/vredsum_vs.h index c4fefe5..c4fefe5 100644 --- a/riscv/insns/vredsum_vv.h +++ b/riscv/insns/vredsum_vs.h diff --git a/riscv/insns/vredxor_vv.h b/riscv/insns/vredxor_vs.h index bb81ad9..bb81ad9 100644 --- a/riscv/insns/vredxor_vv.h +++ b/riscv/insns/vredxor_vs.h diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 65b1288..5891aeb 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -368,14 +368,14 @@ riscv_insn_ext_v_alu_int = \ vor_vi \ vor_vv \ vor_vx \ - vredand_vv \ - vredmax_vv \ - vredmaxu_vv \ - vredmin_vv \ - vredminu_vv \ - vredor_vv \ - vredsum_vv \ - vredxor_vv \ + vredand_vs \ + vredmax_vs \ + vredmaxu_vs \ + vredmin_vs \ + vredminu_vs \ + vredor_vs \ + vredsum_vs \ + vredxor_vs \ vrem_vv \ vrem_vx \ vremu_vv \ @@ -485,7 +485,6 @@ riscv_insn_ext_v_alu_int = \ vxor_vi \ vxor_vv \ vxor_vx \ - riscv_insn_ext_v_alu_fp = \ vfadd_vf \ vfadd_vv \ diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc index 316b667..bf537b0 100644 --- a/spike_main/disasm.cc +++ b/spike_main/disasm.cc @@ -887,14 +887,14 @@ disassembler_t::disassembler_t(int xlen) //OPMVV/OPMVX //0b00_0000 - DISASM_OPIV_V___INSN(vredsum, 1); - DISASM_OPIV_V___INSN(vredand, 1); - DISASM_OPIV_V___INSN(vredor, 1); - DISASM_OPIV_V___INSN(vredxor, 1); - DISASM_OPIV_V___INSN(vredminu, 0); - DISASM_OPIV_V___INSN(vredmin, 1); - DISASM_OPIV_V___INSN(vredmaxu, 0); - DISASM_OPIV_V___INSN(vredmax, 1); + DISASM_OPIV_S___INSN(vredsum, 1); + DISASM_OPIV_S___INSN(vredand, 1); + DISASM_OPIV_S___INSN(vredor, 1); + DISASM_OPIV_S___INSN(vredxor, 1); + DISASM_OPIV_S___INSN(vredminu, 0); + DISASM_OPIV_S___INSN(vredmin, 1); + DISASM_OPIV_S___INSN(vredmaxu, 0); + DISASM_OPIV_S___INSN(vredmax, 1); DISASM_INSN("vext.x.v", vext_x_v, 0, {&xrd, &vs2, &xrs1}); DISASM_INSN("vmv.s.x", vmv_s_x, 0, {&vd, &xrs1}); DISASM_OPIV__X__INSN(vslide1up, 1); |