rvv: add mask register operation

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

9 files changed, 40 insertions, 40 deletions

diff --git a/riscv/decode.h b/riscv/decode.h
index 9280f10..7167529 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -412,6 +412,30 @@ enum VMUNARY0{
   } \
   STATE.VU.vstart = 0;
 
+#define VI_LOOP_MASK(op) \
+  require(STATE.VU.vsew <= e64); \
+  for (reg_t i = STATE.VU.vstart; i < vl; ++i) { \
+    int mlen = STATE>VU.vmlen; \
+    int midx = (mlen * i) / 32; \
+    int mpos = (mlen * i) % 32; \
+    uint32_t mmask = ((1ul << mlen) - 1) << mpos; \
+    uint32_t vs2 = STATE.VU.elt<uint32_t>(insn.rs2(), midx); \
+    uint32_t vs1 = STATE.VU.elt<uint32_t>(insn.rs1(), midx); \
+    \
+    uint32_t res = (res & ~mmask) | ((op) & mmask); \
+    STATE.VU.elt<uint32_t>(insn.rd(), midx) = res; \
+  } \
+  \
+  for (reg_t i = vl; i < STATE.VU.vlmax; ++i) { \
+    int mlen = STATE.VU.vmlen; \
+    int midx = (mlen * i) / 32; \
+    int mpos = (mlen * i) % 32; \
+    uint32_t mmask = ((1ul << mlen) - 1) << mpos; \
+    uint32_t res = (res & ~mmask); \
+    STATE.VU.elt<uint32_t>(insn.rd(), midx) = res; \
+  } \
+  STATE.VU.vstart = 0;
+
 #define VV_U_PARAMS(x) \
     type_usew_t<x>::type &vd = STATE.VU.elt<type_usew_t<x>::type>(rd_num, i); \
     type_usew_t<x>::type vs1 = STATE.VU.elt<type_usew_t<x>::type>(rs1_num, i); \
diff --git a/riscv/insns/vmand_mm.h b/riscv/insns/vmand_mm.h
index e2b73eb..04615c6 100644
--- a/riscv/insns/vmand_mm.h
+++ b/riscv/insns/vmand_mm.h
@@ -1,5 +1,2 @@
-// vmand
-VI_VV_LOOP
-({
-    // NOT IMPLEMENTED YET
-})
+// vmand.mm vd, vs2, vs1
+VI_LOOP_MASK(vs2 & vs1);
diff --git a/riscv/insns/vmandnot_mm.h b/riscv/insns/vmandnot_mm.h
index 6e720b8..4c26469 100644
--- a/riscv/insns/vmandnot_mm.h
+++ b/riscv/insns/vmandnot_mm.h
@@ -1,5 +1,2 @@
-// vmandnot
-VI_VV_LOOP
-({
-    // NOT IMPLEMENTED YET
-})
+// vmandnot.mm vd, vs2, vs1
+VI_LOOP_MASK(vs2 & ~vs1);
diff --git a/riscv/insns/vmnand_mm.h b/riscv/insns/vmnand_mm.h
index f188a12..5a3ab09 100644
--- a/riscv/insns/vmnand_mm.h
+++ b/riscv/insns/vmnand_mm.h
@@ -1,5 +1,2 @@
-// vmnand
-VI_VV_LOOP
-({
-    // NOT IMPLEMENTED YET
-})
+// vmnand.mm vd, vs2, vs1
+VI_LOOP_MASK(~(vs2 & vs1));
diff --git a/riscv/insns/vmnor_mm.h b/riscv/insns/vmnor_mm.h
index 943572b..ab93378 100644
--- a/riscv/insns/vmnor_mm.h
+++ b/riscv/insns/vmnor_mm.h
@@ -1,5 +1,2 @@
-// vmnor
-VI_VV_LOOP
-({
-    // NOT IMPLEMENTED YET
-})
+// vmnor.mm vd, vs2, vs1
+VI_LOOP_MASK(~(vs2 | vs1));
diff --git a/riscv/insns/vmor_mm.h b/riscv/insns/vmor_mm.h
index d696c87..32e71b9 100644
--- a/riscv/insns/vmor_mm.h
+++ b/riscv/insns/vmor_mm.h
@@ -1,5 +1,2 @@
-// vmor
-VI_VV_LOOP
-({
-    // NOT IMPLEMENTED YET
-})
+// vmor.mm vd, vs2, vs1
+VI_LOOP_MASK(vs2 | vs1);
diff --git a/riscv/insns/vmornot_mm.h b/riscv/insns/vmornot_mm.h
index b612728..bdc1d8b 100644
--- a/riscv/insns/vmornot_mm.h
+++ b/riscv/insns/vmornot_mm.h
@@ -1,5 +1,2 @@
-// vmornot
-VI_VV_LOOP
-({
-    // NOT IMPLEMENTED YET
-})
+// vmornot.mm vd, vs2, vs1
+VI_LOOP_MASK(vs2 | ~vs1);
diff --git a/riscv/insns/vmxnor_mm.h b/riscv/insns/vmxnor_mm.h
index 134077a..0736d5b 100644
--- a/riscv/insns/vmxnor_mm.h
+++ b/riscv/insns/vmxnor_mm.h
@@ -1,5 +1,2 @@
-// vmxnor
-VI_VV_LOOP
-({
-    // NOT IMPLEMENTED YET
-})
+// vmnxor.mm vd, vs2, vs1
+VI_LOOP_MASK(~(vs2 ^ vs1));
diff --git a/riscv/insns/vmxor_mm.h b/riscv/insns/vmxor_mm.h
index 6ea260a..7f0c576 100644
--- a/riscv/insns/vmxor_mm.h
+++ b/riscv/insns/vmxor_mm.h
@@ -1,5 +1,2 @@
-// vmxor
-VI_VV_LOOP
-({
-    // NOT IMPLEMENTED YET
-})
+// vmxor.mm vd, vs2, vs1
+VI_LOOP_MASK(vs2 ^ vs1);