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authorJerry Zhao <jerryz123@berkeley.edu>2024-06-20 14:23:01 -0700
committerJerry Zhao <jerryz123@berkeley.edu>2024-06-21 10:29:19 -0700
commit08d5119d3b58463c9951e625663369742808de9c (patch)
treef7dbac1dfc97ed3399eeb27ec1bc82be29ba477c
parenta484f6efc5f50836bb8d846180dfbb9786d09ae2 (diff)
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Relax mstatus.vs dependency on full V
-rw-r--r--riscv/csrs.cc3
-rw-r--r--riscv/processor.h3
2 files changed, 5 insertions, 1 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc
index e985db3..02a2c4f 100644
--- a/riscv/csrs.cc
+++ b/riscv/csrs.cc
@@ -412,7 +412,8 @@ reg_t base_status_csr_t::compute_sstatus_write_mask() const noexcept {
// If a configuration has FS bits, they will always be accessible no
// matter the state of misa.
const bool has_fs = (proc->extension_enabled('S') || proc->extension_enabled('F')) && !proc->extension_enabled(EXT_ZFINX);
- const bool has_vs = proc->extension_enabled('V');
+ // Implementations w/o V may still have mstatus.vs,
+ const bool has_vs = proc->any_vector_extensions();
return 0
| (proc->extension_enabled('S') ? (SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP) : 0)
| (has_page ? (SSTATUS_SUM | SSTATUS_MXR) : 0)
diff --git a/riscv/processor.h b/riscv/processor.h
index 9b776e2..1f11393 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -273,6 +273,9 @@ public:
bool any_custom_extensions() const {
return !custom_extensions.empty();
}
+ bool any_vector_extensions() const {
+ return VU.VLEN > 0;
+ }
bool extension_enabled(unsigned char ext) const {
return extension_enabled(isa_extension_t(ext));
}