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2020-05-25phy: Fix possible NULL pointer deferenceVignesh Raghavendra1-5/+5
It is possible that users of generic_phy_*() APIs may pass a valid struct phy pointer but phy->dev can be NULL, leading to NULL pointer deference in phy_dev_ops(). So call generic_phy_valid() to verify that phy and phy->dev are both valid. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-05-22Merge git://git.denx.de/u-boot-usbTom Rini4-12/+129
- DM support for OMAP - DWC3 fix - Typo fix in eth/r8152
2020-05-22Merge branch 'net' of git://git.denx.de/u-boot-socfpgaTom Rini2-264/+320
- ks8851 cleanups and DM migration
2020-05-22net: ks8851: Add Kconfig entriesMarek Vasut1-0/+14
Convert CONFIG_KS8851_MLL and CONFIG_KS8851_MLL_BASEADDR to Kconfig Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
2020-05-22net: ks8851: Add DM supportMarek Vasut1-0/+103
Add support for U-Boot DM and DT probing. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
2020-05-22net: ks8851: Receive one packet per recv callMarek Vasut1-29/+36
Instead of reading out the entire FIFO and possibly overwriting U-Boot memory, read out one packet per recv call, pass it to U-Boot network stack, and repeat. It is however necessary to cache RXFC value, because reading that one out clears it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
2020-05-22net: ks8851: Split non-DM specific bits from common codeMarek Vasut1-16/+44
Split network handling functions into non-DM specific parts and common code in preparation for conversion to DM. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
2020-05-22net: ks8851: Pass around driver private dataMarek Vasut1-124/+133
Introduce a private data structure for this driver with embedded struct eth_device and pass it around. This prepares the driver to work with both DM and non-DM systems. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
2020-05-22net: ks8851: Checkpatch cleanupMarek Vasut1-9/+10
Fix various checkpatch complaints. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
2020-05-22net: ks8851: Clean up chip ID readoutMarek Vasut1-19/+2
There is only one chip ID in the table of chip IDs for this chip. Read out the chip ID instead and mask off the last "revision" bit to check the chip ID, this works for all chips in the family. Then drop the chip ID passing around. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
2020-05-22net: ks8851: Remove type_frame_headMarek Vasut1-29/+7
The packet status and length information should be extracted from the FIFO per-packet. Adjust the code such that it reads the packet meta data and then the packet afterward, if applicable. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
2020-05-22net: ks8851: Trim down struct ks_netMarek Vasut1-61/+9
Most of the entries in the structure are useless, remove them. Inline the rest of uses where applicable. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
2020-05-22net: ks8851: Use 16bit RXQCR accessMarek Vasut1-13/+4
Per KS8851-16MLL, the RXQCR is a 16bit register. Use 16bit accessors to it consistently and drop the ks_wrreg8() function altogether, as it is not used anymore. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
2020-05-22net: ks8851: Remove RXQCR cacheMarek Vasut1-9/+6
The cached RXQCR value is never updated, remove the cache and just use the bits in the cache directly in the code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
2020-05-22net: ks8851: Replace malloc()+memset() with calloc()Marek Vasut1-6/+3
Replace combination of malloc()+memset() with calloc() as the behavior is exactly the same and the amount of code is reduced. Moreover, remove printf() in the fail path, as it is useless, and return proper -ENOMEM return code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
2020-05-22Merge tag 'u-boot-rockchip-20200522' of ↵Tom Rini6-0/+1001
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Fix rk3288 chromebook veyron support; - Add pcie driver support for rk3399; - other fixes for rk3399 boards
2020-05-22Merge tag 'imx8qxp-fixes' of ↵Tom Rini2-26/+28
https://gitlab.denx.de/u-boot/custodians/u-boot-video - Fix i.MX8QXP boot hang when getting CPU temperature
2020-05-22eth/r8152: fix typo in register nameHayes Wang2-6/+6
The PAL_BDC_CR should be PLA_BDC_CR. Signed-off-by: Hayes Wang <hayeswang@realtek.com>
2020-05-22usb: dwc3: fix NULL pointer issueChunfeng Yun1-3/+3
The phy_bulk pointer *usb_phys is used before allocated, fix it by using a phy_bulk variable instead in xhci_dwc3_platdata struct Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2020-05-22usb: ehci-omap: Add Support for DM_USB and OF_CONTROLAdam Ford1-3/+120
The omap3.dtsi file shows the usbhshost node with two sub-nodes for ohci and ehci. This patch file creates the usbhshost, and pulls the portX-mode information. It then locates the EHCI sub-node, and initializes the EHCI controller with the info pulled from the usbhshost node. There is still more to do since there isn't an actual link between the 'phys' reference and the corresponding phy driver, and there is no nop-xceiv driver yet. In the meantime, the older style reference to CONFIG_OMAP_EHCI_PHYx_RESET_GPIO is still needed to pull the phy out of reset until the phy driver is completed and the phandle reference is made. Signed-off-by: Adam Ford <aford173@gmail.com>
2020-05-22pci: Add Rockchip PCIe PHY controller driverJagan Teki4-14/+306
Yes, it is possible to have a dedicated UCLASS PHY driver for this Rockchip PCIe PHY but there are some issues on Generic PHY framework to support the same. The Generic PHY framework is unable to get the PHY if the PHY parent is of a different uclass. Say if we try to get the PCIe PHY then the phy-uclass will look for PHY in the first instance if it is not in the root node it will try to probe the parent by assuming that the actual PHY is inside the parent PHY of UCLASS_PHY. But, in rk3399 hardware representation PHY like emmc, usb and pcie are part of syscon which is completely a different of UCLASS_SYSCON. Example: grf: syscon@ff770000 { compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x10000>; #address-cells = <1>; #size-cells = <1>; pcie_phy: pcie-phy { compatible = "rockchip,rk3399-pcie-phy"; clocks = <&cru SCLK_PCIEPHY_REF>; clock-names = "refclk"; #phy-cells = <1>; resets = <&cru SRST_PCIEPHY>; drive-impedance-ohm = <50>; reset-names = "phy"; status = "disabled"; }; }; Due to this limitation, this patch adds a separate PHY driver for Rockchip PCIe. This might be removed in future once Generic PHY supports this limitation. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22pci: Add Rockchip PCIe controller driverJagan Teki4-0/+555
Add Rockchip PCIe controller driver for rk3399 platform. Driver support Gen1 by operating as a Root complex. Thanks to Patrick for initial work. Signed-off-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
2020-05-22clk: rk3399: Enable/Disable the PCIEPHY clkJagan Teki1-0/+6
Enable/Disable the PCIEPHY clk for rk3399. CLK is clear in both enable and disable functionality. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22clk: rk3399: Add enable/disable clksJagan Teki1-0/+148
Yes, most of the high speed peripheral clocks in rk3399 enabled by default. But it would be better to handle them via clk enable/disable API for handling proper reset conditions like 'usb reset' over command line. So, enable USB, GMAC clock via enable/disable ops. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Suniel Mahesh <sunil.m@amarulasolutions.com> # roc-rk3399-pc Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22thermal: imx_scu_thermal: prevent boot hang with zero pdataAnatolij Gustschin1-1/+3
Should initialization of pdata values have failed for some reason, we end up in endless loop when getting the CPU temperature value and can not boot. Check alert value in pdata and only retry reading temperature if alert value is not zero. Also shorten the temperature info string. Signed-off-by: Anatolij Gustschin <agust@denx.de>
2020-05-22cpu: imx8: use intended cpu-thermal device when getting temp valueAnatolij Gustschin1-25/+25
This fixes getting DT alert and critical pdata values in imx_scu_thermal driver. On i.MX8QXP using not initialized alert pdata value resulted in boot hang and endless loop outputting: CPU Temperature (47200C) has beyond alert (0C), close to critical (0C) waiting... While at it, preset CPU type values once to avoid multiple calls of device_is_compatible() for same property. Fixes: 3ee6ea443eb4 ("cpu: imx_cpu: Print the CPU temperature for iMX8QM A72") Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-05-22cpu: imx8: fix type and rate detectionAnatolij Gustschin1-6/+6
CPU type and rate detection is broken, for A35 cpu we get A53: ... sc_pm_get_clock_rate: resource:0 clk:2: res:3 Could not read CPU frequency: -22 CPU: NXP i.MX8QXP RevB A53 at 0 MHz at 47C Fixes: 55bc96f3b675 ("cpu: imx8: fix get core name and rate") Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-05-22mtd: rawnand: denali: deassert write protect pinMasahiro Yamada1-0/+1
[ Linux commit 9afbe7c0140f663586edb6e823b616bd7076c00a ] If the write protect signal from this IP is connected to the NAND device, this IP can handle the WP# pin via the WRITE_PROTECT register. The Denali NAND Flash Memory Controller User's Guide describes this register like follows: When the controller is in reset, the WP# pin is always asserted to the device. Once the reset is removed, the WP# is de-asserted. The software will then have to come and program this bit to assert/de-assert the same. 1 - Write protect de-assert 0 - Write protect assert The default value is 1, so the write protect is de-asserted after the reset is removed. The driver can write to the device unless someone has explicitly cleared register before booting the kernel. The boot ROM of some UniPhier SoCs (LD4, Pro4, sLD8, Pro5) is the case; the boot ROM clears the WRITE_PROTECT register when the system is booting from the NAND device, so the NAND device becomes read-only. Set it to 1 in the driver in order to allow the write access to the device. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2020-05-22mtd: rawnand: denali: configure SPARE_AREA_SKIP_BYTES only for denali_splMasahiro Yamada1-9/+9
This CONFIG option is only used in denali_spl.c Move it close to SPL_NAND_DENALI, and make it depend on SPL_NAND_DENALI. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-05-20Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini2-5/+31
- Add DM_ETH support for lx2160aqds, ls2080aqds, ls1088aqds - QSI related fixes on ls1012a, ls2080a, ls1046a, ls1088a, ls1043a based platforms - Bug-fixes/updtaes related to ls1046afrwy, fsl-mc, msi-map property
2020-05-19drivers: crypto: mod_exp_sw: Re-add DM_FLAG_PRE_RELOCJan Kiszka1-0/+1
This driver is safe to use in SPL without relocation. Denying DM_FLAG_PRE_RELOC prevents its usability for verifying the main U-Boot or other artifacts from the SPL unless needless enabling the full driver set (SPL_OF_PLATDATA). Fixes: 17e117408571 ("drivers: crypto: rsa_mod_exp: avoid DM_FLAG_PRE_RELOC") CC: Heinrich Schuchardt <xypron.glpk@gmx.de> CC: Marek Vasut <marex@denx.de> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2020-05-19net: fsl-mc: fixup DPC: add /board/ports node if missingRazvan Ionut Cirjan1-3/+14
The DPC fixup for MAC address and enet_if is not made if /board/ports node is missing in DPC file. Add /board/ports or /ports nodes if them are missing. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> Reviewed-by: Ioana Ciornei <Ioana.ciornei@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-19drivers: net: fsl-mc: fixup msi-map propertyLaurentiu Tudor1-1/+16
Similarly to iommu-map, the msi-map property must also be fixed up in the device tree, in order for the icid -> streamid translation be possible in the MSI case as well. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Diana Craciun <diana.craciun@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-19driver: net: fm: minor fix in DM ETH supportMadalin Bucur1-1/+1
Bus callback functions for read/write/reset need to be set only for DM_ETH, moving endif a bit lower. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass438-0/+444
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop linux/delay.h from common headerSimon Glass452-0/+452
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18Fix some checkpatch warnings in calls to udelay()Simon Glass9-60/+60
Fix up some incorrect code style in calls to functions in the linux/time.h header, mostly udelay(). Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop linux/stringify.h from common headerSimon Glass6-0/+6
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop linux/bug.h from common headerSimon Glass67-0/+67
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop asm/ptrace.h from common headerSimon Glass3-0/+3
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop log.h from common headerSimon Glass832-2/+837
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18Fix some checkpatch warnings in calls to debug()Simon Glass1-6/+6
Fix up some incorrect code style in calls to functions in the log.h header, mostly debug(). Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18command: Remove the cmd_tbl_t typedefSimon Glass33-63/+92
We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop init.h from common headerSimon Glass31-0/+31
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop image.h from common headerSimon Glass18-1/+21
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop bootstage.h from common headerSimon Glass8-0/+8
Move this fairly uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop part.h from common headerSimon Glass34-1/+40
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18part: Drop disk_partition_t typedefSimon Glass3-13/+13
We should not be using typedefs and these make it harder to use forward declarations (to reduce header file inclusions). Drop the typedef. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop net.h from common headerSimon Glass92-0/+104
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18arm: Don't include common.h in header filesSimon Glass3-0/+11
It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-07-20 07:43:23 +0000