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| author | Jagan Teki <jagan@amarulasolutions.com> | 2020-05-09 22:26:20 +0530 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2020-05-22 20:53:20 +0800 |
| commit | 912f633d01334b006b9594404a1feed336efd10b (patch) | |
| tree | 90bd77c573e83718b2afa0cc2525971cfde71e23 /drivers | |
| parent | 30d09a2f17e82cb893dc3720490f4bed0fb225db (diff) | |
| download | u-boot-912f633d01334b006b9594404a1feed336efd10b.zip u-boot-912f633d01334b006b9594404a1feed336efd10b.tar.gz u-boot-912f633d01334b006b9594404a1feed336efd10b.tar.bz2 | |
clk: rk3399: Enable/Disable the PCIEPHY clk
Enable/Disable the PCIEPHY clk for rk3399.
CLK is clear in both enable and disable functionality.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3399.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 371410d..6a78837 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1139,6 +1139,9 @@ static int rk3399_clk_enable(struct clk *clk) case HCLK_HOST1_ARB: rk_clrreg(&priv->cru->clksel_con[20], BIT(8)); break; + case SCLK_PCIEPHY_REF: + rk_clrreg(&priv->cru->clksel_con[18], BIT(10)); + break; default: debug("%s: unsupported clk %ld\n", __func__, clk->id); return -ENOENT; @@ -1212,6 +1215,9 @@ static int rk3399_clk_disable(struct clk *clk) case HCLK_HOST1_ARB: rk_setreg(&priv->cru->clksel_con[20], BIT(8)); break; + case SCLK_PCIEPHY_REF: + rk_clrreg(&priv->cru->clksel_con[18], BIT(10)); + break; default: debug("%s: unsupported clk %ld\n", __func__, clk->id); return -ENOENT; |