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5 daysMerge patch series "vbe: Series part D"Tom Rini1-0/+9
Simon Glass <sjg@chromium.org> says: This includes various patches towards implementing the VBE abrec bootmeth in U-Boot.
5 daysram: Support driver model in VPLSimon Glass1-0/+9
Some boards want to use RAM in VPL so add an option for that. Signed-off-by: Simon Glass <sjg@chromium.org>
8 daysMerge tag 'v2024.10-rc6' into nextTom Rini1-2/+3
Prepare v2024.10-rc6
2024-09-24ram: k3-ddrss: Handle error properly in lpddr4_startUdit Kumar1-2/+3
In lpddr4_start function error returned by lpddr4_enablepiinitiator may go undetected due to overwrite of return code. Add support to handle error in above case. Reported-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com>
2024-09-11ram: ast2700: Add DRAM controller initializationChia-Wei Wang6-5/+10691
Add driver for AST2700 to initialize DRAM in SPL. This patch also refactors the Kconfig dependency of Aspeed DRAM drivers as some of them are shared among the file structures of RV and ARM ISAs. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-08-05rockchip: Avoid #ifdefs in RK3399 SPLSimon Glass1-19/+21
The code here is confusing due to large blocks which are #ifdefed out. Add a function phase_sdram_init() which returns whether SDRAM init should happen in the current phase, using that as needed to control the code flow. This increases code size by about 500 bytes in SPL when the cache is on, since it must call the rather large rockchip_sdram_size() function. Signed-off-by: Simon Glass <sjg@chromium.org>
2024-08-05rockchip: Ensure memory size is available in RK3399 SPLSimon Glass1-8/+14
At present gd->ram_size is 0 in SPL, meaning that it is not possible to enable the cache. Correct this by always populating the RAM size correctly. This increases code size by about 500 bytes in SPL, since it must call the rather large rockchip_sdram_size() function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2024-07-22drivers: ram: Remove duplicate newlinesMarek Vasut3-6/+0
Drop all duplicate newlines. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-06-19ram: k3-ddrss: Enable the am62ax's DDR controller for J722SJayesh Choudhary1-1/+1
The J722S family of SoCs uses the same DDR controller as found on the AM62A family. Enable this option when building for the J722S family. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2024-05-20Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"WIP/20May2024-nextTom Rini41-40/+22
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-19Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""Tom Rini41-22/+40
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-07ram: Remove <common.h> and add needed includesTom Rini41-40/+22
Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
2024-04-26rockchip: rk3308: Move cru and grf include files to arch-rockchipJonas Karlman1-1/+1
Move cru_rk3308.h and grf_rk3308.h to arch-rockchip to match path used for all other Rockchip SoCs. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-03-15Merge tag 'u-boot-rockchip-20240315' of ↵WIP/15Mar2024-nextTom Rini8-8/+3
https://source.denx.de/u-boot/custodians/u-boot-rockchip into next Please pull the updates for rockchip platform: - Add board: rk3588 Generic, Cool Pi CM5, Theobroma-Systems RK3588 Jaguar SBC, Toybrick TB-RK3588X; rk3588s Cool Pi 4B; rk3566 Pine64 PineTab2; - Add saradc v2 support; - Add PMIC RK806 support; - rk3588 disable force_jtag by default; - Migrate to use IO-domain driver for all boards; - Use common bss and stack addresses for rk33xx and rk35xx boards; - Other updates for driver, config and dts;
2024-03-13ram: k3-ddrss: enable the am62ax's DDR controller for am62pxBryan Brattlof1-1/+1
The am62px family of SoCs uses the same DDR controller as found on the am62ax family. Enable this option when building for the am62px family Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
2024-03-13rockchip: include asm/io.h directly in asm/arch-rockchip/hardware.hQuentin Schulz8-8/+0
The different macros use writel which is defined in asm/io.h, so let's include the header so users of hardware.h do not need to include asm/io.h as well. While at it, remove asm/io.h includes wherever asm/arch-rockchip/hardware.h is included already. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2024-03-13rockchip: migrate hardware.h inclusion into appropriate filesQuentin Schulz3-0/+3
hardware.h is only defining macros which are "wrappers" around writel(). writel() is however not available in hardware.h, <asm/io.h> needs to be included. This means in order to use the wrappers in hardware.h, one also needs to include the <asm/io.h> header. However, this cannot be done currently because hardware.h is included in include/configs files, which are implicitly included by every code file by default, which makes the compilation of arch/arm/cpu/armv8/u-boot.lds fail because ALIGN (the ARM assembly directive) got redefined by some of the include files coming from <asm.io.h>. Because nothing in the include/configs file actually use hardware.h, let's remove the inclusion of hardware.h from the include/configs files and explicitly add it wherever it is required. This prepares for the next commit where <asm/io.h> will be included in hardware.h. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2024-03-11Merge tag 'v2024.04-rc4' into nextTom Rini1-1/+1
Prepare v2024.04-rc4
2024-03-04arm: mach-k3: Add basic support for J784S4 SoC definitionApurva Nandan1-1/+1
Add J784S4 initialization files for initial SPL boot. config SYS_K3_MCU_SCRATCHPAD_BASE default value is same for J721E, J721S2, J784S4. So combined them into a single default. Signed-off-by: Hari Nagalla <hnagalla@ti.com> [ add firewall configurations and change the R5 MCU scratchpad ] Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
2024-03-02ARM: renesas: Rename ARCH_RMOBILE to ARCH_RENESASMarek Vasut1-1/+1
Rename ARCH_RMOBILE to ARCH_RENESAS because all the chips are made by Renesas, while only a subset of them is from the R-Mobile line. Use the following command to perform the rename: " $ git grep -l 'ARCH_RMOBILE' | xargs -I {} sed -i 's@ARCH_RMOBILE@ARCH_RENESAS@g' {} " Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-02-04ram: rockchip: Add rv1126 ddr4 supportTim Lunn8-0/+533
Add support for ddr4 on rv1126. Timing detection files are imported from downstream Rockchip BSP u-boot. Allow selecting ddr4 ram with define CONFIG_RAM_ROCKCHIP_DDR4. Signed-off-by: Tim Lunn <tim@feathertop.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-11-10tree-wide: Replace http:// link with https:// link for ti.comNishanth Menon4-4/+4
Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-10-22sunxi: add R528/T113-s3/D1(s) DRAM initialisation codeAndre Przywara5-0/+1574
The Allwinner R528/T113-s/D1/D1s SoCs all share the same die, so use the same DRAM initialisation code. Make use of prior art here and lift some code from awboot[1], which carried init code based on earlier decompilation efforts, but with a GPL2 license tag. This code has been heavily reworked and cleaned up, to match previous DRAM routines for other SoCs, and also to be closer to U-Boot's coding style and support routines. The actual DRAM chip timing parameters are included in the main file, since they cover all DRAM types, and are protected by a new Kconfig CONFIG_SUNXI_DRAM_TYPE symbol, which allows the compiler to pick only the relevant settings, at build time. The relevant DRAM chips/board specific configuration parameters are delivered via Kconfig, so this code here should work for all supported SoCs and DRAM chips combinations. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Sam Edwards <CFSworks@gmail.com>
2023-10-22Kconfig: sunxi: prepare for using drivers/ram/sunxiAndre Przywara2-1/+8
At the moment all Allwinner DRAM initialisation routines are stored in arch/arm/mach-sunxi, even though those "drivers" are just a giant collection of writel's, without any architectural dependency. The R528/T113-s SoC (with ARM cores) and the D1/D1s Soc (with RISC-V cores) share the same die, so should share the same DRAM init routines as well. To prepare for this, add a new sunxi directory inside drivers/ram, and add some stub entries to prepare for the addition of the share DRAM code for those SoCs. The RISC-V D1(s) SoCs will probably use SPL_DM, so for that SoC this would be the right directory anyway. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-10-13treewide: use dev_read_addr_*_ptr() where appropriateMatthias Schiffer2-23/+20
A follow-up to commit 842fb5de424e ("drivers: use devfdt_get_addr_size_index_ptr when cast to pointer") and commit 320a1938b6f7 ("drivers: use devfdt_get_addr_index_ptr when cast to pointer"). In addition to using the *_ptr variants of these functions where the address is cast to a pointer, this also changes devfdt_get_addr_*() to dev_read_addr_*() in a few places. Some variable and field types are changed from fdt_addr_t or phys_addr_t to void* where the cast was happening later. This patch fixes a number of compile warnings when building a 32bit U-Boot with CONFIG_PHYS_64BIT=y. In some places, it also fixes error handling where the return value of dev_read_addr() etc. was checked for NULL instead of FDT_ADDR_T_NONE. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-04Merge tag 'u-boot-stm32-20231004' of ↵Tom Rini1-1/+2
https://source.denx.de/u-boot/custodians/u-boot-stm STM32 MCU: _ alignment with kernel DT v6.5 for stm32f429 and stm32f746 _ rework way of displaying ST logo for stm32f746-disco and stm32f769-disco STM32 MPU: _ alignment with kernel DT v6.6-rc1 _ add RNG support for stm32mp13 _ add USB, USB boot and stm32prog command support for stm32mp13 _ add support of USART1 clock for stm32mp1 _ only print RAM and board code with SPL_DISPLAY_PRINT flag for stm32mp1 _ rename update_sf to dh_update_sd_to_sf and add dh_update_sd_to_emmc for stm32mp15xx DHCOR [ Fix merge conflict at board/st/common/stm32mp_dfu.c ] Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-04ram: stm32mp1: Only print RAM config with CONFIG_SPL_DISPLAY_PRINTHarald Seiler1-1/+2
Ensure that the RAM configuration line is only printed when CONFIG_SPL_DISPLAY_PRINT is set. Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-09-24common: Drop linux/printk.h from common headerSimon Glass5-0/+5
This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-08-03board: mediatek: update config headersWeijie Gao1-0/+1
Remove unused information from include/configs/mtxxxx.h Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-07-21ram: k3-ddrss: do not touch ctrl regs during trainingBryan Brattlof1-7/+4
During LPDDR initialization we will loop through a series of frequency changes in order to train at the various operating frequencies. During this training, accessing the DRAM_CLASS bitfield could happen during a frequency change and cause the read to hang. Store the DRAM type into the main structure to avoid multiple readings while the independent phy is training. Signed-off-by: Bryan Brattlof <bb@ti.com>
2023-07-12ram: starfive: Read memory size information from EEPROMYanhong Wang1-2/+0
StarFive VisionFive 2 has two versions, 1.2A and 1.3B, each version of DDR capacity includes 2G/4G/8G, a DT can not support multiple capacities, so the capacity size information is recorded to EEPROM, when DDR initialization required capacity size information is read from EEPROM. If there is no information in EEPROM, it is initialized with the default size defined in DT. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-05-13board: schneider: add RZN1 board supportRalph Siemsen4-0/+383
Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which are based on the Reneasas RZ/N1 SoC devices. The intention is to support both boards using a single defconfig, and to handle the differences at runtime. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13ram: cadence: add driver for Cadence EDACRalph Siemsen5-0/+430
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-06core: remap: fix regmap_init_mem_plat() reg size handelingJohan Jonker6-6/+6
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so convert regmap_init_mem_plat() input to handel both. The syscon class driver also makes use of the regmap_init_mem_plat() function, but has no way of knowing the format of the device-specific platform data. In case of odd reg structures other then that the syscon class driver assumes the regmap must be filled in the individual syscon driver before pre-probe. Also fix the ARRAY_SIZE divider in the syscon class driver. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-24arm: mach-k3: Remove empty sys_proto.h includeAndrew Davis1-1/+0
This header file is now empty, remove it. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-04-24arm: mach-k3: Move sdelay() and wait_on_value() declarationAndrew Davis1-0/+4
These probably should be in some system wide header given their use. Until then move them out of K3 sys_proto.h so we can finish cleaning that header out. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-04-23Merge tag 'u-boot-rockchip-20230421' of ↵WIP/23Apr2023Tom Rini1-0/+2
https://source.denx.de/u-boot/custodians/u-boot-rockchip - Add rk3588 evb support; - Update pinctrl for rk3568 and rk3588; - Update rk3288 dts; - Update mmc support for rk3568 and rk3588; - Add rng support for rk3588; - Add DSI support for rk3568; - Some other misc fixes in dts, config, driver;
2023-04-22Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini10-1/+3202
* Add StarFive VisionFive v2 Board support * Support CONFIG_REMAKE_ELF * Code cleanups for RISC-V architecture
2023-04-21ram: rk3399: add missing high row detectionJonathan Liu1-0/+2
For 2 GB LPDDR4 single-rank RAM with 16 rows, the Rockchip ddr init bin prints: "Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB" U-Boot TPL prints: "BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB" Add missing high row detection so that U-Boot TPL prints Row=16, same as the Rockchip ddr init bin: "BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB" Signed-off-by: Jonathan Liu <net147@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-20ram: starfive: add ddr driverYanhong Wang10-1/+3202
Add driver for StarFive JH7110 to support ddr initialization in SPL. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-19stm32mp: fix various array bounds checksRasmus Villemoes1-1/+1
In all these cases, the index on the LHS is immediately afterwards used to access the array appearing in the ARRAY_SIZE() on the RHS - so if that index is equal to the array size, we'll access one-past-the-end of the array. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-04-03Merge branch 'next'Tom Rini1-3/+3
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-04-02rockchip: Fix incorrect constant name in RAM init codeWIP/02Apr2023David Sebek1-1/+1
A condition in the rk3399 RAM initialization code used the old CONFIG_RAM_RK3399_LPDDR4 constant name. This commit changes the condition to use the correct CONFIG_RAM_ROCKCHIP_LPDDR4 constant. Reviewed-by: Simon Glass <sjg@chromium.org>
2023-03-14Merge tag 'v2023.04-rc4' into nextTom Rini2-0/+58
Prepare v2023.04-rc4 Signed-off-by: Tom Rini <trini@konsulko.com>
2023-03-06ram: ast2600: Keep MPLL power onDylan Hung1-3/+3
According to the PLL vendor, we should keep the PLL power on, so we shouldn't toggle the power-down bit during PLL initialization. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au>
2023-02-28ram: rockchip: Add rk3588 ddr driver supportJagan Teki2-0/+58
Add ddr driver for rk3588 to get the ram capacity. Co-developed-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-20global: Finish CONFIG -> CFG migrationTom Rini3-11/+11
At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-16ram: rockchip: Add rv1126 lpddr4 supportJagan Teki8-0/+556
Add LPDDR4 detection timings and support for RV1126. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16ram: rockchip: rv1126: Control ddr init prints via DEBUGJagan Teki1-13/+25
Control the ddr init print messages via RAM_ROCKCHIP_DEBUG instead of printing by default. This gives an option to configs to enable these prints or not. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16ram: rockchip: Add rv1126 ddr driver supportJagan Teki2-0/+3522
Add DDR driver for Rockchip RV1126 SoC. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
generated by cgit v1.1 at 2024-10-09 01:18:16 +0000