aboutsummaryrefslogtreecommitdiff
path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2019-01-09clk: imx8: fix build warningPeng Fan1-0/+2
2018-12-29clk: uniphier: add NAND 200MHz clockMasahiro Yamada1-3/+5
2018-12-06clk: stm32: add hardware spinlock clockBenjamin Gaignard1-0/+3
2018-12-06clk: Allow clock defaults to be set during re-reloc state for SPL onlyPhilipp Tomsich1-0/+4
2018-12-03Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini1-7/+3
2018-12-03ARM: meson: Add regmap support for clock driverLoic Devulder1-29/+30
2018-12-03clk: renesas: Allow reconfiguring SDHI clock on Gen3Marek Vasut1-7/+3
2018-11-30rockchip: rk3399: Initialize CPU B clock.Christoph Muellner1-9/+70
2018-11-30ARM: rockchip: rv1108: Sync clock with vendor treeOtavio Salvador1-6/+469
2018-11-29Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogicTom Rini3-4/+320
2018-11-28clk: MediaTek: add clock driver for MT7623 SoC.Ryder Lee2-0/+871
2018-11-28clk: MediaTek: add clock driver for MT7629 SoC.Ryder Lee5-0/+1403
2018-11-26clk: Add clock driver for AXGNeil Armstrong2-1/+317
2018-11-26ARM: meson: rework soc arch file to prepare for new SoCJerome Brunet1-1/+1
2018-11-26clk: meson: silence debug printJerome Brunet1-1/+1
2018-11-26clk: meson: add static to meson_gates tableNeil Armstrong1-1/+1
2018-11-20misc: Update read() and write() methods to return bytes xferedSimon Glass1-2/+2
2018-11-20clk: meson: fix clk81 divider calculationJerome Brunet1-1/+2
2018-11-16clk: Allow clock defaults to be set also during re-reloc stateAndreas Dannenberg1-4/+0
2018-11-14clk: Remove DM_FLAG_PRE_RELOC flag in various driversBin Meng5-7/+0
2018-11-05aspeed: ast2500: fix D2-PLL clock setting in RGMII modeCédric Le Goater1-0/+38
2018-11-05aspeed: ast2500: fix missing break in D2PLL clock enablementCédric Le Goater1-0/+1
2018-10-28drivers: cosmetic: Convert SPDX license tags to Linux Kernel stylePatrick Delaunay6-10/+7
2018-10-22clk: imx: add clk driver for i.MX8QXPPeng Fan5-0/+406
2018-09-30clk: Add support for Arm's Versatile Express OSC clock generatorsLiviu Dudau3-0/+117
2018-09-19Merge git://git.denx.de/u-boot-marvellTom Rini1-1/+129
2018-09-19clk: armada-37xx-periph: Support changing clock parent and rateMarek Behún1-1/+129
2018-09-18clk: Add MPC83xx clock driverMario Six4-0/+796
2018-09-11clk: Introduce TI System Control Interface (TI SCI) clock driverAndreas Dannenberg3-0/+226
2018-09-10clk: clk_meson: Add mux and div support for reparent and rate settingNeil Armstrong1-5/+528
2018-08-20Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini1-4/+4
2018-08-17Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini3-0/+371
2018-08-13clk: socfpga: Add initial Arria10 clock driverMarek Vasut3-0/+371
2018-08-13clk: at91: utmi: add timeout for utmi lockEugen Hristev1-1/+6
2018-08-10clk: Kconfig: Ascending order to sub directiory kconfigsJagan Teki1-4/+4
2018-08-04clk: clk_set_default: accept no-op skip fieldsNeil Armstrong1-0/+8
2018-08-03clk: add clk_valid()Fabrice Gasnier1-0/+13
2018-07-20stm32mp1: clk: support digital bypassPatrick Delaunay1-9/+18
2018-07-20stm32mp1: clk: add ADC clock gatingPatrick Delaunay1-0/+7
2018-07-20stm32mp1: clk: update Ethernet clock gatingPatrick Delaunay1-2/+1
2018-07-20stm32mp1: clk: add LDTC and DSI clock supportPatrick Delaunay1-3/+93
2018-07-20stm32mp1: clk: add common function pll_get_fvcoPatrick Delaunay1-30/+61
2018-07-20stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macroPatrick Delaunay1-9/+6
2018-07-20misc: stm32: Add STM32MP1 supportPatrick Delaunay1-6/+0
2018-07-19clk: zynqmp: Fixed the same if/else part error reported by coverityVipul Kumar1-2/+4
2018-07-09clk: Add Actions Semi OWL clock supportManivannan Sadhasivam5-0/+155
2018-06-19clk: add Amlogic meson clock driverBeniamino Galvani3-0/+441
2018-06-14clk: rmobile: Add R8A77995 RPC clockMarek Vasut1-0/+5
2018-06-14clk: rmobile: Add R8A77990 RPC clockMarek Vasut1-0/+5
2018-06-02Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini5-32/+386
generated by cgit v1.1 at 2024-07-10 17:33:12 +0000