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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2019-02-09clk: stm32mp1: correctly handle Clock Spreading GeneratorPatrick Delaunay1-1/+7
2019-02-09clk: stm32mp1: add debug informationPatrick Delaunay1-4/+79
2019-02-09clk: stm32mp1: recalculate counter when switching freqPatrick Delaunay1-2/+7
2019-02-09clk: stm32mp1: correct access to RCC_OCENSETR/RCC_OCENCLRRPatrick Delaunay1-8/+5
2019-02-09clk: stm32mp1: add IPCC clockPatrick Delaunay1-0/+1
2019-02-09clk: stm32mp1: no more get ck_usbo_48m in device treePatrick Delaunay1-3/+3
2019-02-01rockchip: clk: Add mention of four new clocksSimon Glass1-0/+12
2019-02-01clk: Improve debug message in clk_set_default_rates()Simon Glass1-2/+2
2019-02-01rockchip: rk3288: Add i2s pinctrl and clock supportSimon Glass1-0/+48
2019-01-30sunxi: clk: enable clk and reset for CCU devicesAndre Przywara1-0/+12
2019-01-29sunxi: clk: A80: add MMC clock supportAndre Przywara1-1/+27
2019-01-29sunxi: clk: add MMC gates/resetsAndre Przywara11-0/+63
2019-01-18clk: sunxi: Add Allwinner A80 CLK driverJagan Teki3-0/+65
2019-01-18clk: sunxi: Add Allwinner H6 CLK driverJagan Teki3-0/+61
2019-01-18clk: sunxi: Implement UART resetsJagan Teki7-0/+43
2019-01-18clk: sunxi: Implement UART clocksJagan Teki9-0/+57
2019-01-18clk: sunxi: Add Allwinner V3S CLK driverJagan Teki3-0/+59
2019-01-18clk: sunxi: Add Allwinner R40 CLK driverJagan Teki3-0/+78
2019-01-18clk: sunxi: Add Allwinner A83T CLK driverJagan Teki3-0/+71
2019-01-18clk: sunxi: Add Allwinner A23/A33 CLK driverJagan Teki3-0/+71
2019-01-18clk: sunxi: Add Allwinner A31 CLK driverJagan Teki3-0/+76
2019-01-18clk: sunxi: Add Allwinner A10s/A13 CLK driverJagan Teki3-0/+64
2019-01-18clk: sunxi: Add Allwinner A10/A20 CLK driverJagan Teki3-0/+67
2019-01-18clk: sunxi: Add Allwinner H3/H5 CLK driverJagan Teki3-0/+87
2019-01-18reset: Add Allwinner RESET driverJagan Teki2-0/+21
2019-01-18clk: Add Allwinner A64 CLK driverJagan Teki6-0/+149
2019-01-14clk: MediaTek: bind ethsys reset controllerWeijie Gao3-0/+32
2019-01-09clk: imx8: fix build warningPeng Fan1-0/+2
2018-12-29clk: uniphier: add NAND 200MHz clockMasahiro Yamada1-3/+5
2018-12-06clk: stm32: add hardware spinlock clockBenjamin Gaignard1-0/+3
2018-12-06clk: Allow clock defaults to be set during re-reloc state for SPL onlyPhilipp Tomsich1-0/+4
2018-12-03Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini1-7/+3
2018-12-03ARM: meson: Add regmap support for clock driverLoic Devulder1-29/+30
2018-12-03clk: renesas: Allow reconfiguring SDHI clock on Gen3Marek Vasut1-7/+3
2018-11-30rockchip: rk3399: Initialize CPU B clock.Christoph Muellner1-9/+70
2018-11-30ARM: rockchip: rv1108: Sync clock with vendor treeOtavio Salvador1-6/+469
2018-11-29Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogicTom Rini3-4/+320
2018-11-28clk: MediaTek: add clock driver for MT7623 SoC.Ryder Lee2-0/+871
2018-11-28clk: MediaTek: add clock driver for MT7629 SoC.Ryder Lee5-0/+1403
2018-11-26clk: Add clock driver for AXGNeil Armstrong2-1/+317
2018-11-26ARM: meson: rework soc arch file to prepare for new SoCJerome Brunet1-1/+1
2018-11-26clk: meson: silence debug printJerome Brunet1-1/+1
2018-11-26clk: meson: add static to meson_gates tableNeil Armstrong1-1/+1
2018-11-20misc: Update read() and write() methods to return bytes xferedSimon Glass1-2/+2
2018-11-20clk: meson: fix clk81 divider calculationJerome Brunet1-1/+2
2018-11-16clk: Allow clock defaults to be set also during re-reloc stateAndreas Dannenberg1-4/+0
2018-11-14clk: Remove DM_FLAG_PRE_RELOC flag in various driversBin Meng5-7/+0
2018-11-05aspeed: ast2500: fix D2-PLL clock setting in RGMII modeCédric Le Goater1-0/+38
2018-11-05aspeed: ast2500: fix missing break in D2PLL clock enablementCédric Le Goater1-0/+1
2018-10-28drivers: cosmetic: Convert SPDX license tags to Linux Kernel stylePatrick Delaunay6-10/+7