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2020-04-15board: stm32mp1: correct CONFIG_IS_ENABLED usage for LEDPatrick Delaunay2-2/+2
Use the correct macro to test presence CONFIG_LED: replace CONFIG_IS_ENABLED(CONFIG_LED) by CONFIG_IS_ENABLED(LED) Issue see during review unrelated patch "board: stm32mp1: update management of boot-led" http://patchwork.ozlabs.org/patch/1264823/ Cc: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-04-15configs: stm32mp1: replace STM32MP1_TRUSTED by TFABOOTPatrick Delaunay2-4/+4
Activate ARCH_SUPPORT_TFABOOT and replace the arch stm32mp specific config CONFIG_STM32MP1_TRUSTED by the generic CONFIG_TFABOOT introduced by the commit 535d76a12150 ("armv8: layerscape: Add TFABOOT support"). This config CONFIG_TFABOOT is activated for the trusted boot chain, when U-Boot is loaded by TF-A. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-04-15ARM: dts: stm32: Add KS8851-16MLL ethernet on FMC2Marek Vasut1-0/+52
Add DT entries, Kconfig entries and board-specific entries to configure FMC2 bus and make KS8851-16MLL on that bus accessible to U-Boot. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-04-14arm: mvebu: turris_mox: fix PCIe ranges in device treeMarek Behún1-0/+11
Use the new a3700_fdt_fix_pcie_regions function in turris_mox.c so that MOX boards with 4 GB RAM are fully supported. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14arm: mvebu: turris_mox: support devices with RAM > 1 GBMarek Behún1-16/+0
In order to support MOX boards with 2 GB or 4 GB RAM, we use the new Armada-3700 generic code for memory information structures. This is done by removing dram_init and dram_init_banksize from turris_mox.c, in order for the generic, weak definitions to be used. Also for boards with 4 GB RAM it is needed to increase CONFIG_NR_DRAM_BANKS to 2 in turris_mox_defconfig. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14arm: mvebu: turris_mox: sort headers alphabeticallyMarek Behún1-8/+8
Sort #includes alphabetically, the only exception is common.h, which is included first in most parts of U-Boot. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14arm: mvebu: turris_mox: don't use hardcoded addressesMarek Behún2-11/+14
Use macro MVEBU_REGISTER to access register addresses instead of hardcoded addresses. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14arm: mvebu: turris_mox: Setup Linux's device tree before bootMarek Behún1-18/+277
Patch Linux's device tree according to which Mox modules are connected. Linux's device tree has all possible Mox module nodes preprogrammed, but in disabled state. If MOX B, MOX F or MOX G module is present, this code enables the PCI node. For the network modules (MOX C, MOX D and MOX E) are present, the code enables corresponding ethernet and swtich nodes and DSA connections. For the SFP cage the SFP GPIO controller node and SFP node are also enabled. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14arm: mvebu: turris_mox: Fix early SPI communicationMarek Behún1-3/+6
The SPI clock signal changes value when the SPI configuration register is configured. This can sometimes lead to the device misinterpreting the enablement of the SPI controller as actual clock tick. This can be solved by first setting the SPI CS1 pin from GPIO to SPI mode, and only after that writing the SPI configuration register. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14arm: mvebu: clearfog: Use Pro DT by defaultJoel Johnson1-1/+1
Switch to explicitly using the Pro variant DT, which has been available since Linux 4.11. Signed-off-by: Joel Johnson <mrjoel@lixil.net> Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14arm: mvebu: clearfog: move ENV params to KconfigJoel Johnson1-0/+8
Migrate the values for ENV_SIZE and ENV_OFFSET into board specific Kconfig defaults so they're more accessible for configuration. Signed-off-by: Joel Johnson <mrjoel@lixil.net> Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14arm: mvebu: clearfog: add SPI offsetsJoel Johnson1-0/+12
Add reasonable default SPI offsets and ENV size when configured to boot from SPI flash. Signed-off-by: Joel Johnson <mrjoel@lixil.net> Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14arm: mvebu: clearfog: Unify DT selection pathsJoel Johnson1-0/+2
Unify the location of DT selection into board_late_init instead of split between detection and static configuration paths. Signed-off-by: Joel Johnson <mrjoel@lixil.net> Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14arm: mvebu: clearfog: Add SATA mode flagsJoel Johnson2-0/+31
The mPCIe slots on ClearFog Pro and ClearFog Base may be alternately configured for SATA usage. Signed-off-by: Joel Johnson <mrjoel@lixil.net> Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14arm: mvebu: clearfog: Add option for 2.5 Gbps SFPJoel Johnson2-0/+12
While newer Linux kernels provide autoconfiguration of SFP, provide an option for setting in U-Boot Kconfig for use prior to booting. Signed-off-by: Joel Johnson <mrjoel@lixil.net> Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14arm: mvebu: clearfog: initial ClearFog Base variantJoel Johnson2-6/+50
Add a unique entry for ClearFog Base variant, reflected in the board name and adjusted SerDes topology. Signed-off-by: Joel Johnson <mrjoel@lixil.net> Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14arm: mvebu: clearfog: use Pro name by defaultJoel Johnson1-1/+1
Make the board version printed indicate the Pro variant default. Also adjust static name casing to match what is expected for EEPROM product name to share string constants. Signed-off-by: Joel Johnson <mrjoel@lixil.net> Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-14ddr: marvell: a38x: Allow boards to specify CK_DELAY parameterChris Packham1-1/+5
For some layouts it is necessary to adjust the CK_DELAY parameter to successfully complete DDR training. Add the ability to specify the CK_DELAY in the mv_ddr_topology_map. Signed-off-by: Chris Packham <judge.packham@gmail.com>
2020-04-13Merge branch 'next'Tom Rini16-48/+2301
Pull in changes that have been pending in our 'next' branch. This includes: - A large number of CI improvements including moving to gcc-9.2 for all platforms. - amlogic, xilinx, stm32, TI SoC updates - USB and i2c subsystem updtaes - Re-sync Kbuild/etc logic with v4.19 of the Linux kernel. - RSA key handling improvements
2020-04-08Merge tag 'u-boot-amlogic-20200406' of ↵Tom Rini1-0/+2
https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic into next - clk: meson-g12a: missing break - sync all Amlogic DT from Linux v5.6-rc2 - MMC clock fixups - add support for Libre Computer AML-S905D-PC and AML-S912-PC
2020-04-07Merge tag 'xilinx-for-v2020.07' of ↵Tom Rini23-1174/+2466
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2020.07 common: - Align ENV_FAT_INTERFACE - Fix MAC address source print log - Improve based autodetection code xilinx: - Enable netconsole Microblaze: - Setup default ENV_OFFSET/ENV_SECT_SIZE Zynq: - Multiple DT updates/fixes - Use DEVICE_TREE environment variable for DTB selection - Switch to single zynq configuration - Enable NOR flash via DM - Minor SPL print removal - Enable i2c mux driver ZynqMP: - Print multiboot register - Enable cache commands in mini mtest - Multiple DT updates/fixes - Fix firmware probing when driver is not enabled - Specify 3rd backup RAM boot mode in SPL - Add SPL support for zcu102 v1.1 and zcu111 revA - Redesign debug uart enabling and psu_init delay - Enable full u-boot run from EL3 - Enable u-boot.itb generation without ATF with U-Boot in EL3 Versal: - Enable distro default - Enable others SPI flashes - Enable systems without DDR Drivers: - Gem: - Flush memory after freeing - Handle mdio bus separately - Watchdog: - Get rid of unused global data pointer - Enable window watchdog timer - Serial: - Change reinitialization logic in zynq serial driver Signed-off-by: Tom Rini <trini@konsulko.com>
2020-04-07colibri_imx6: set gpr1 ENET_CLK_SELIgor Opaniuk1-0/+3
This fixes the issue when PHY auto negotiation never completes. Fixes: 431cd76dd8("colibri_imx6: migrate to DM_ETH") Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-04-06arm64: xilinx: Never touch DDR if system has no DDRMichal Simek1-1/+5
If DDR is not mapped do not touch it. Default XILINX_OF_BOARD_DTB_ADDR is pointing to DDR. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06arm64: zynqmp: Reorder parameters for zynqmp_mmio_write()Michal Simek1-1/+1
Parameter order is not correct based on zynqmp_mmio_write() declaration. Fixes: be52372ff1bb ("arm64: zynqmp: Use zynqmp_mmio_read/write functions") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06arm64: zynqmp: Move timeout for clock propagation below psu_initMichal Simek1-0/+3
Delay required for clock propagation is tighly coupled with initialization done in psu_init(). That's why call it also for u-boot proper with CONFIG_ZYNQMP_PSU_INIT_ENABLED enabled. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06arm64: zynqmp: Add support for debug uart also for U-Boot properMichal Simek1-3/+12
board_early_init_f() is the right location where debug uart can be configurated (after MIO initialization). The patch is taking this call from SPL to also make it available for U-Boot proper. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06arm64: zynqmp Add support for zcu111 revAMichal Simek1-0/+978
Add low level configuration for zcu111 for easier SPL run. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06arm64: zynqmp Add support for zcu102 rev1.1Michal Simek1-0/+1042
rev1.1 has different DDR sodimm module that's why it requires different DDR configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06arm64: zynqmp: Check firmware node when driver is enabledMichal Simek1-0/+2
ZynqMP mini configurations works without PMU firmware that's why there is no reason to enable the driver and check if it was probed properly. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06arm64: zynqmp: Print multiboot register value in EL3Michal Simek1-0/+14
Multi boot register can be used for using different boot images and design better boot strategy. Let EL3 SPL or U-Boot to read it and print it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06arm64: dts: meson: add libretech-pc supportJerome Brunet1-0/+2
Add support for the Amlogic based libretech-pc platform. This platform comes with 2 variant, based on the s905d or s912 SoC. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> [narmstrong: update board/amlogic/q200/MAINTAINERS] Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-02ARM: tegra: Add NVIDIA Jetson Nano Developer Kit supportTom Warren4-0/+204
The Jetson Nano Developer Kit is a Tegra X1-based development board. It is similar to Jetson TX1 but it is not pin compatible. It features 4GB of LPDDR4, a SPI NOR flash for early boot firmware and an SD card slot used for storage. HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0 and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI Ethernet controller provides onboard network connectivity. NVMe support has also been added. Env save is at the end of QSPI (4MB-8K). A 40-pin header on the board can be used to extend the capabilities and exposed interfaces of the Jetson Nano. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Tested-by: Peter Robinson <pbrobinson@gmail.com>
2020-04-02t210: pinmux: Remove pinmux/GPIO init from T210 boardsTom Warren8-1143/+4
T210 CBoot is now doing the full pinmux and GPIO init, based on the DTB tables. Remove pinmux/GPIO init tables & code from all T210-based builds below: p2371-2180 aka TX1 p2371-0000 e2220-1170 p2571 Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2020-04-01Merge tag 'u-boot-stm32-20200401' of ↵Tom Rini1-8/+7
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Fix device tree of Avenger96 board from Arrow Electronics and add compatibility with stm32mp15_dhcom_basic_defconfig
2020-04-01ARM: dts: stm32: Use DT alias for the configuration EEPROMMarek Vasut1-8/+7
Use DT /aliases node to establish a stable phandle to the configuration EEPROM. This permits the configuration EEPROM to be moved e.g. to a different address or a different bus. Adjust the board code to handle new phandle lookup. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-03-31Merge branch 'next' of git://git.denx.de/u-boot-usb into nextTom Rini2-9/+7
2020-03-31Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini1-0/+22
- Fixes for Gen 2 V2H Blanche
2020-03-30ARM: rmobile: Only register ethernet on V2H Blanche if not DM_ETHMarek Vasut1-0/+2
If the DM_ETH is enabled, the board-specific ethernet registeration should be disabled, make it so. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-03-30ARM: rmobile: Implement PMIC reset on V2H BlancheMarek Vasut1-0/+20
Add code to reset the board through PMIC, by writing the required PMIC registers in the CPU reset handler. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-03-30configs: ls1012ardb: secure boot: Add PFE configPriyanka Singh1-1/+1
Add config to enable the PFE and ETH support. Also change the pfe secure boot header address. Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30dm: arm64: ls1046a: add i2c DM supportBiwen Li2-6/+36
This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1046A Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30dm: arm64: ls1043a: add i2c DM supportBiwen Li1-6/+92
This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1043A Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30board: fsl: lx2160a: fix SDHC1_DAT4 signal routingYangbo Lu1-3/+9
The SDHC1_DAT4 signal could be routes to SDHC1_VS or SDHC1 adapter slot for SDHC1 usage. When SDHC1 is selected in RCW, do not force to route it to SDHC1 adapter slot if find it has already been configued for SDHC1_VS. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30lx2160a : Remove default VID settingMeenakshi Aggarwal1-1/+8
Set VID to 800 mV for Rev1 and set VID as per switch settings for Rev2. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30board: fsl: lx2160a: Add GIC LPI memory reserve fixupWasim Khan1-0/+16
Reserve DDR memory region used for GIC LPI configuration table. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30board: fsl: lx2160a: Program GIC LPI configuration tableWasim Khan1-1/+9
Program GIC LPI configuration table: 1. Redistributor PROCBASER configuration table (which is common for all redistributors) 2. Redistributor pending table (PENDBASER), for all the available redistributors. Signed-off-by: Manish Tomar <manish.tomar@nxp.com> Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30board: lx2160a: Correct board fixup for PCIe nodesVikas Singh1-0/+1
Update "board_fix_fdt" with correct counter value "i". This will fix the issue while fetching the "reg_names" resource from fdt after fixup. Signed-off-by: Vikas Singh <vikas.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-26elgin-rv1108: Use rk_board_late_init() for GPIO settingsOtavio Salvador1-1/+1
Since commit 8e9a8d0d0c8c ("rockchip: elgin-rv1108: use board_early_init_f for per-boar init") the function that configure the board GPIOs is no longer called since CONFIG_BOARD_EARLY_INIT_F=y is not selected. These GPIOs do not need to be configured in such early stagem, so change it to rk_board_late_init() and also select CONFIG_BOARD_LATE_INIT=y to fix the regression. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-03-26rockchip: evb-rv1108: Use syscon API to get grf baseKever Yang1-4/+3
Use syscon API to get grf base instead of get from dts. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-03-26rockchip: elgin-rv1108: Use syscon API to get grf baseKever Yang1-4/+3
Use syscon API to get grf base instead of get from dts. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
generated by cgit v1.1 at 2024-09-06 01:11:13 +0000