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AgeCommit message (Expand)AuthorFilesLines
2015-01-23x86: Support ROMs on other archsSimon Glass1-0/+2
2015-01-13x86: fsp: Drop get_hob_type() and get_hob_length()Bin Meng2-34/+4
2015-01-13x86: ivybridge: Update microcode early in bootSimon Glass1-0/+6
2015-01-13x86: Add support for MTRRsSimon Glass2-83/+89
2015-01-13x86: Drop RAMTOP KconfigSimon Glass1-8/+0
2015-01-12x86: Simplify the fsp hob access functionsBin Meng2-30/+21
2015-01-12pci: Make pci apis usable before relocationBin Meng2-2/+1
2014-12-18x86: Clean up the FSP support codesBin Meng9-134/+140
2014-12-18x86: crownbay: Add SPI flash supportBin Meng1-0/+15
2014-12-18x86: ich6-gpio: Add Intel Tunnel Creek GPIO supportBin Meng2-2/+15
2014-12-18x86: Add basic support to queensbay platform and crownbay boardBin Meng1-0/+3
2014-12-15x86: move arch-specific asmlinkage to <asm/linkage.h>Masahiro Yamada3-1/+8
2014-12-13x86: Support Intel FSP initialization path in start.SBin Meng1-0/+3
2014-12-13x86: Add post failure codes for bist and carBin Meng1-0/+2
2014-12-13x86: queensbay: Adapt FSP support codesBin Meng1-1/+1
2014-12-13x86: Initial import from Intel FSP release for Queensbay platformBin Meng10-0/+1096
2014-12-13x86: Add a simple superio driver for SMSC LPC47MBin Meng1-0/+90
2014-12-13x86: ich6-gpio: Move setup_pch_gpios() to board support codesBin Meng3-0/+7
2014-12-08Replace <compiler.h> with <linux/compiler.h>Masahiro Yamada3-3/+3
2014-11-25x86: Add initial video device init for Intel GMASimon Glass1-0/+2
2014-11-25x86: Add GDT descriptors for option ROMsSimon Glass1-19/+12
2014-11-25x86: ivybridge: Add northbridge init functionsSimon Glass2-1/+16
2014-11-25x86: Drop some msr functions that we don't supportSimon Glass1-11/+0
2014-11-25x86: Add init for model 206AX CPUSimon Glass2-0/+5
2014-11-25x86: Add LAPIC setup codeSimon Glass2-2/+123
2014-11-25x86: Refactor interrupt_init()Bin Meng1-0/+2
2014-11-25x86: Remove cpu_init_r() for x86Bin Meng1-2/+0
2014-11-25x86: Add Intel speedstep and turbo mode codeSimon Glass2-0/+120
2014-11-25x86: ivybridge: Set up XHCI USBSimon Glass1-0/+1
2014-11-25x86: ivybridge: Set up EHCI USBSimon Glass1-0/+1
2014-11-25x86: ivybridge: Add SATA initSimon Glass2-0/+60
2014-11-25x86: ivybridge: Add PCH initSimon Glass1-0/+49
2014-11-25x86: Add a simple header file for ACPISimon Glass1-0/+24
2014-11-25x86: ivybridge: Add support for BD82x6x PCHSimon Glass2-0/+27
2014-11-25x86: Set up edge triggering on interrupt 9Simon Glass1-0/+11
2014-11-25x86: pci: Add handlers before and after a PCI hose scanSimon Glass1-0/+3
2014-11-25x86: Add ioapic.h headerSimon Glass1-0/+38
2014-11-21x86: ivybridge: Implement SDRAM initSimon Glass8-0/+613
2014-11-21x86: ivybridge: Add LAPIC supportSimon Glass2-0/+160
2014-11-21x86: ivybridge: Add support for early GPIO initSimon Glass4-6/+158
2014-11-21x86: ivybridge: Add early init for PCH devicesSimon Glass4-1/+237
2014-11-21x86: ivybridge: Perform Intel microcode update on bootSimon Glass1-0/+20
2014-11-21x86: ivybridge: Perform initial CPU setupSimon Glass3-0/+144
2014-11-21x86: Add msr read/write functions that use a structureSimon Glass1-0/+19
2014-11-21x86: Add clr/setbits functionsSimon Glass1-0/+49
2014-11-21x86: ivybridge: Add early LPC init so that serial worksSimon Glass1-0/+48
2014-11-21x86: pci: Allow configuration before relocationSimon Glass1-0/+13
2014-11-21x86: Support use of PCI before relocationSimon Glass2-0/+10
2014-11-21x86: Refactor PCI to permit alternate initSimon Glass1-0/+11
2014-11-21x86: chromebook_link: Implement CAR support (cache as RAM)Simon Glass2-1/+133
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